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/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dpalmbus.yaml19 pattern: "^palmbus(@[0-9a-f]+)?$"
37 "@[0-9a-f]+$":
62 reg = <0x1e000000 0x100000>;
65 ranges = <0x0 0x1e000000 0x0fffff>;
72 gpio-ranges = <&pinctrl 0 0 95>;
74 reg = <0x600 0x100>;
/freebsd/sys/contrib/device-tree/Bindings/mtd/partitions/
H A Dbrcm,bcm963xx-imagetag.txt18 reg = <0x1e000000 0x2000000>;
26 cfe@0 {
27 reg = <0x0 0x10000>;
32 reg = <0x10000 0x7d0000>;
37 reg = <0x7e0000 0x10000>;
42 reg = <0x7f0000 0x10000>;
/freebsd/sys/contrib/device-tree/src/mips/mti/
H A Dmalta.dts7 /memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
8 /memreserve/ 0x00001000 0x000ef000; /* YAMON */
9 /memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
25 reg = <0x1bdc0000 0x20000>;
56 reg = <0x1e000000 0x400000>;
66 yamon@0 {
68 reg = <0x0 0x100000>;
74 reg = <0x100000 0x2e0000>;
79 reg = <0x3e0000 0x20000>;
87 reg = <0x1f000000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/broadcom/
H A Dbcm53016-dlink-dwl-8610ap.dts13 memory@0 {
16 reg = <0x00000000 0x08000000>,
17 <0x88000000 0x08000000>;
26 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
66 * Flash memory at 0x1e000000-0x1fffffff
72 reg = <0x1e080000 0x00020000>;
112 trx@0 {
114 reg = <0x00000000 0x02800000>;
121 reg = <0x02800000 0x02800000>;
128 reg = <0x05000000 0x03000000>;
H A Dbcm47094-dlink-dir-890l.dts31 memory@0 {
33 reg = <0x00000000 0x08000000>,
34 <0x88000000 0x08000000>;
46 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
108 * The flash memory is memory mapped at 0x1e000000-0x1fffffff
114 reg = <0x1e1f000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Darm,pl172.txt11 first address cell and it may accept values 0..N-1
88 Example for pl172 with nor flash on chip select 0 shown below.
92 reg = <0x40005000 0x1000>;
97 ranges = <0 0 0x1c000000 0x1000000
98 1 0 0x1d000000 0x1000000
99 2 0 0x1e000000 0x1000000
100 3 0 0x1f000000 0x1000000>;
107 mpmc,cs = <0>;
110 mpmc,write-enable-delay = <0>;
111 mpmc,output-enable-delay = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/ralink/
H A Dmt7621.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0>;
33 #address-cells = <0>;
149 reg = <0x1e000000 0x100000>;
150 ranges = <0x0 0x1e000000 0x0fffff>;
155 sysc: syscon@0 {
157 reg = <0x0 0x100>;
171 reg = <0x100 0x100>;
177 reg = <0x600 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-pba8.dts29 arm,hbi = <0x178>;
33 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0>;
46 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
56 reg = <0x1e001000 0x1000>,
57 <0x1e000000 0x100>;
63 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
68 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
81 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
[all …]
H A Dvexpress-v2p-ca9.dts16 arm,hbi = <0x191>;
17 arm,vexpress,site = <0xf>;
38 #size-cells = <0>;
40 A9_0: cpu@0 {
43 reg = <0>;
71 reg = <0x60000000 0x40000000>;
79 /* Chipselect 3 is physically at 0x4c000000 */
83 reg = <0x4c000000 0x00800000>;
90 reg = <0x10020000 0x1000>;
92 interrupts = <0 44 4>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm6358.dtsi13 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
33 #clock-cells = <0>;
47 #address-cells = <0>;
63 reg = <0xfffe0004 0x4>;
69 reg = <0xfffe0008 0x4>;
74 offset = <0x0>;
75 mask = <0x1>;
81 reg = <0xfffe000c 0x8>,
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211desc.h31 uint32_t ds_ctl0; /* DMA control 0 */
33 uint32_t ds_status0; /* DMA status 0 */
40 #define AR_FrameLen 0x00000fff /* frame length */
42 #define AR_XmitRate 0x003c0000 /* txrate */
44 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS enable */
45 #define AR_VEOL 0x00800000 /* virtual end-of-list */
46 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
47 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
49 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
50 #define AR_EncryptKeyValid 0x40000000 /* EncryptKeyIdx is valid */
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp2041rdb.dts67 size = <0 0x1000000>;
68 alignment = <0 0x1000000>;
71 size = <0 0x400000>;
72 alignment = <0 0x400000>;
75 size = <0 0x2000000>;
76 alignment = <0 0x2000000>;
81 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
85 ranges = <0x0 0xf 0xf4000000 0x200000>;
89 ranges = <0x0 0xf 0xf4200000 0x200000>;
93 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dp2020ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 ramdisk@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
55 reg = <0x03e00000 0x00200000>;
60 reg = <0x04000000 0x00400000>;
65 reg = <0x04400000 0x03b00000>;
69 reg = <0x07f00000 0x00080000>;
74 reg = <0x07f80000 0x00080000>;
[all …]
H A Dp5020ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x2000000>;
77 alignment = <0 0x2000000>;
82 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
86 ranges = <0x0 0xf 0xf4000000 0x200000>;
90 ranges = <0x0 0xf 0xf4200000 0x200000>;
94 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Dp3041ds.dts68 size = <0 0x1000000>;
69 alignment = <0 0x1000000>;
72 size = <0 0x400000>;
73 alignment = <0 0x400000>;
76 size = <0 0x200000
[all...]
H A Dp5040ds.dts80 size = <0 0x1000000>;
81 alignment = <0 0x1000000>;
84 size = <0 0x400000>;
85 alignment = <0 0x400000>;
88 size = <0 0x200000
[all...]
H A Dmpc8572ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00060000>;
77 reg = <0x07f60000 0x00020000>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212desc.h32 uint32_t ds_ctl0; /* DMA control 0 */
38 uint32_t status0;/* DMA status 0 */
42 uint32_t status0;/* DMA status 0 */
58 #define AR_FrameLen 0x00000fff /* frame length */
60 #define AR_XmitPower 0x003f0000 /* transmit power control */
62 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
63 #define AR_VEOL 0x00800000 /* virtual end-of-list */
64 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
65 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
67 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416desc.h29 #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
68 uint32_t ds_ctl0; /* DMA control 0 */
104 #define AR_FrameLen 0x00000fff
105 #define AR_VirtMoreFrag 0x00001000
106 #define AR_TxCtlRsvd00 0x0000e000
107 #define AR_XmitPower 0x003f0000
109 #define AR_RTSEnable 0x00400000
110 #define AR_VEOL 0x00800000
111 #define AR_ClrDestMask 0x01000000
112 #define AR_TxCtlRsvd01 0x1e000000
[all …]
/freebsd/sys/dts/arm/
H A Dvybrid.dtsi56 bus-frequency = <0>;
60 reg = <0x4006E000 0x100>;
65 reg = <0x40001000 0x1000>;
70 reg = <0x40003000 0x1000>, /* Distributor Registers */
71 <0x40002100 0x100>; /* CPU Interface Registers */
78 reg = <0x40050000 0x300>;
83 reg = <0x4006b000 0x1000>;
91 #size-cells = <0>;
92 reg = < 0x40002200 0x100 >, /* Global Timer Registers */
93 < 0x40002600 0x100 >; /* Private Timer Registers */
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041ds.dts60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portal@0 {
93 buffer-pool@0 {
95 fsl,bpid = <0>;
96 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
101 qportal0: qman-portal@0 {
188 flash@0 {
192 reg = <0>;
196 reg = <0x00000000 0x00100000>;
[all …]
H A Dp5020ds.dts60 reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
64 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
68 bman-portal@0 {
91 buffer-pool@0 {
93 fsl,bpid = <0>;
94 fsl,bpool-cfg = <0 0x100 0 1 0 0x100>;
99 qportal0: qman-portal@0 {
184 flash@0 {
188 reg = <0>;
192 reg = <0x00000000 0x00100000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap3-n950-n9.dtsi12 cpu@0 {
19 reg = <0x80000000 0x40000000>; /* 1 GB */
47 pinctrl-0 = <&debug_leds>;
54 #clock-cells = <0>;
62 OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */
63 OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */
69 OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */
75 OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */
76 OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd */
77 OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0 */
[all …]

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