| /freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
| H A D | imx8mm-phygate-tauri-l.dts | 26 #clock-cells = <0>;
32 pinctrl-0 = <&pinctrl_gpiokeys>;
44 pinctrl-0 = <&pinctrl_leds>;
71 pinctrl-0 = <&pinctrl_usbhubpwr>;
82 pinctrl-0 = <&pinctrl_usbotg1pwr>;
94 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
106 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
108 #size-cells = <0>;
112 can0: can@0 {
114 reg = <0>;
[all …]
|
| H A D | imx8mp-msc-sm2s.dtsi | 25 pinctrl-0 = <&pinctrl_usb0_vbus>;
36 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
70 lcd0_backlight: backlight-0 {
73 pinctrl-0 = <&pinctrl_lcd0_backlight>;
74 pwms = <&pwm1 0 100000 0>;
75 brightness-levels = <0 255>;
85 pinctrl-0 = <&pinctrl_lcd1_backlight>;
86 pwms = <&pwm2 0 100000 0>;
87 brightness-levels = <0 255>;
[all …]
|
| H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
|
| H A D | imx8mm-phycore-som.dtsi | 21 reg = <0x0 0x40000000 0 0x80000000>;
76 pinctrl-0 = <&pinctrl_fec1>;
81 #size-cells = <0>;
83 ethphy0: ethernet-phy@0 {
90 reg = <0>;
101 pinctrl-0 = <&pinctrl_flexspi0>;
104 som_flash: flash@0 {
[all...] |
| H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
|
| H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
|
| H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,qmp-ufs-phy.yaml | 68 "^phy@[0-9a-f]+$":
77 const: 0
168 "^phy@[0-9a-f]+$":
186 "^phy@[0-9a-f]+$":
204 "^phy@[0-9a-f]+$":
218 reg = <0x01d87000 0xe10>;
221 ranges = <0x0 0x01d87000 0x1000>;
226 resets = <&ufs_mem_hc 0>;
233 reg = <0x400 0x108>,
234 <0x600 0x1e0>,
[all …]
|
| H A D | qcom,msm8996-qmp-ufs-phy.yaml | 70 "^phy@[0-9a-f]+$":
82 const: 0
172 "^phy@[0-9a-f]+$":
191 "^phy@[0-9a-f]+$":
206 reg = <0x01d87000 0x1c0>;
209 ranges = <0x0 0x01d87000 0x1000>;
214 resets = <&ufs_mem_hc 0>;
221 reg = <0x400 0x108>,
222 <0x600 0x1e0>,
223 <0xc00 0x1dc>,
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | ti,iodelay.txt | 24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/display/msm/ |
| H A D | dsi-phy-14nm.yaml | 63 reg = <0x0ae94400 0x200>,
64 <0x0ae94600 0x280>,
65 <0x0ae94a00 0x1e0>;
71 #phy-cells = <0>;
|
| H A D | qcom,sm7150-mdss.yaml | 52 "^display-controller@[0-9a-f]+$":
59 "^displayport-controller@[0-9a-f]+$":
66 "^dsi@[0-9a-f]+$":
75 "^phy@[0-9a-f]+$":
97 reg = <0x0ae00000 0x1000>;
125 iommus = <&apps_smmu 0x800 0x440>;
133 reg = <0x0ae01000 0x8f000>,
134 <0x0aeb0000 0x2008>;
157 interrupts = <0>;
161 #size-cells = <0>;
[all …]
|
| H A D | dsi-phy-10nm.yaml | 82 reg = <0x0ae94400 0x200>,
83 <0x0ae94600 0x280>,
84 <0x0ae94a00 0x1e0>;
90 #phy-cells = <0>;
97 qcom,phy-rescode-offset-top = /bits/ 8 <0 0
[all...] |
| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
|
| H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
|
| H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
|
| /freebsd/tools/test/stress2/misc/ |
| H A D | snap2.sh | 29 [ `id -u ` -ne 0 ] && echo "Must be root!" && exit 1
33 # panic(c088cd33,deadc000,c0943aa0,0,c08753e1) at panic+0x14b
34 # vm_fault(c1060000,deadc000,1,0,c54de480) at vm_fault+0x1e0
35 # trap_pfault(e76728b8,0,deadc112) at trap_pfault+0x137
36 # trap(8,c0870028,28,deadc0de,deadc0de) at trap+0x355
37 # calltrap() at calltrap+0x5
38 # --- trap 0xc, eip = 0xc060bcfb, esp = 0xe76728f8, ebp = 0xe767291c ---
39 # g_io_request(c53ff7bc,c5051d40,d8c72408,c54ca110,e7672950) at g_io_request+0x5f
43 mount | grep -q "on /tmp (ufs," || exit 0
45 trap "rm -f /tmp/.snap/stress2" 0
|
| H A D | snap2-1.sh | 29 [ `id -u ` -ne 0 ] && echo "Must be root!" && exit 1
35 # panic(c088cd33,deadc000,c0943aa0,0,c08753e1) at panic+0x14b
36 # vm_fault(c1060000,deadc000,1,0,c54de480) at vm_fault+0x1e0
37 # trap_pfault(e76728b8,0,deadc112) at trap_pfault+0x137
38 # trap(8,c0870028,28,deadc0de,deadc0de) at trap+0x355
39 # calltrap() at calltrap+0x5
40 # --- trap 0xc, eip = 0xc060bcfb, esp = 0xe76728f8, ebp = 0xe767291c ---
41 # g_io_request(c53ff7bc,c5051d40,d8c72408,c54ca110,e7672950) at g_io_request+0x5f
43 mount | grep -q "on /tmp (ufs," || exit 0
46 trap "rm -f /tmp/.snap/stress2" 0
|
| H A D | mount.sh | 34 # Stopped at kdb_enter+0x2b: nop
36 # Tracing pid 69453 tid 100388 td 0xc4b5c1b0
37 # kdb_enter(c091d9db) at kdb_enter+0x2b
38 # panic(c0938fa0,deadc000,e6b44834,c06c650e,c0a57d20,...) at panic+0x14b
39 # vm_fault(c1869000,deadc000,1,0) at vm_fault+0x1e0
40 # trap_pfault(e6b4499c,0,deadc112) at trap_pfault+0x137
41 # trap(8,c0910028,28,deadc0de,deadc0de,...) at trap+0x3f5
42 # calltrap() at calltrap+0x5
43 # --- trap 0xc, eip = 0xc0667def, esp = 0xe6b449dc, ebp = 0xe6b44a00 ---
44 # g_io_request(c66d6bdc,c4a1d840,d7c99940,d7c99940,e6b44a34,...) at g_io_request+0x5f
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Support/BLAKE3/ |
| H A D | blake3_avx2_x86-64_windows_gnu.S | 20 and rsp, 0xFFFFFFFFFFFFFFC0
21 vmovdqa xmmword ptr [rsp+0x2D0], xmm6
22 vmovdqa xmmword ptr [rsp+0x2E0], xmm7
23 vmovdqa xmmword ptr [rsp+0x2F0], xmm8
24 vmovdqa xmmword ptr [rsp+0x300], xmm9
25 vmovdqa xmmword ptr [rsp+0x310], xmm10
26 vmovdqa xmmword ptr [rsp+0x320], xmm11
27 vmovdqa xmmword ptr [rsp+0x330], xmm12
28 vmovdqa xmmword ptr [rsp+0x340], xmm13
29 vmovdqa xmmword ptr [rsp+0x350], xmm14
[all …]
|
| H A D | blake3_avx2_x86-64_unix.S | 47 and rsp, 0xFFFFFFFFFFFFFFC0
51 vmovdqa ymmword ptr [rsp+0x280], ymm0
54 vmovdqa ymmword ptr [rsp+0x220], ymm2
58 vmovdqa ymmword ptr [rsp+0x240], ymm2
66 vmovdqa ymmword ptr [rsp+0x260], ymm3
68 mov qword ptr [rsp+0x2A0], rdx
73 vpbroadcastd ymm1, dword ptr [rcx+0x4]
74 vpbroadcastd ymm2, dword ptr [rcx+0x8]
75 vpbroadcastd ymm3, dword ptr [rcx+0xC]
76 vpbroadcastd ymm4, dword ptr [rcx+0x10]
[all …]
|
| /freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/blake3/ |
| H A D | blake3_avx2.S | 47 and rsp, 0xFFFFFFFFFFFFFFC0
51 vmovdqa ymmword ptr [rsp+0x280], ymm0
54 vmovdqa ymmword ptr [rsp+0x220], ymm2
58 vmovdqa ymmword ptr [rsp+0x240], ymm2
66 vmovdqa ymmword ptr [rsp+0x260], ymm3
68 mov qword ptr [rsp+0x2A0], rdx
73 vpbroadcastd ymm1, dword ptr [rcx+0x4]
74 vpbroadcastd ymm2, dword ptr [rcx+0x8]
75 vpbroadcastd ymm3, dword ptr [rcx+0xC]
76 vpbroadcastd ymm4, dword ptr [rcx+0x10]
[all …]
|
| /freebsd/sys/dev/bhnd/ |
| H A D | bhndreg.h | 32 #define BHND_DEFAULT_CHIPC_ADDR 0x18000000
38 #define BHND_DEFAULT_CORE_SIZE 0x1000
43 #define BHND_DEFAULT_ENUM_SIZE 0x00100000
56 #define BHND_CLK_CTL_ST 0x1e0 /**< clock control and status */
57 #define BHND_CCS_FORCEALP 0x00000001 /**< force ALP request */
58 #define BHND_CCS_FORCEHT 0x00000002 /**< force HT request */
59 #define BHND_CCS_FORCEILP 0x00000004 /**< force ILP request */
60 #define BHND_CCS_FORCE_MASK 0x0000000F
62 #define BHND_CCS_ALPAREQ 0x00000008 /**< ALP Avail Request */
63 #define BHND_CCS_HTAREQ 0x00000010 /**< HT Avail Request */
[all …]
|
| /freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
| H A D | vf610-pinfunc.h | 14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
|
| /freebsd/sys/contrib/dev/mediatek/mt76/ |
| H A D | mt76x02_eeprom.h | 13 MT_EE_CHIP_ID = 0x000,
14 MT_EE_VERSION = 0x002,
15 MT_EE_MAC_ADDR = 0x004,
16 MT_EE_PCI_ID = 0x00A,
17 MT_EE_ANTENNA = 0x022,
18 MT_EE_CFG1_INIT = 0x024,
19 MT_EE_NIC_CONF_0 = 0x034,
20 MT_EE_NIC_CONF_1 = 0x036,
21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,
22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,
[all …]
|