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/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-mx8menlo.dts22 pinctrl-0 = <&pinctrl_led>;
40 pinctrl-0 = <&pinctrl_beeper>;
47 #clock-cells = <0>;
54 #size-cells = <0>;
56 pinctrl-0 = <&pinctrl_ecspi1>;
61 canfd: can@0 {
66 reg = <0>;
73 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
77 spidev@0 {
79 reg = <0>;
[all …]
H A Dimx8mp-verdin.dtsi25 brightness-levels = <0 45 63 88 119 158 203 255>;
30 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
33 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
39 brightness-levels = <0 45 63 88 119 158 203 255>;
44 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
53 pinctrl-0 = <&pinctrl_usb_1_id>;
68 pinctrl-0 = <&pinctrl_gpio_keys>;
73 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
117 pinctrl-0 = <&pinctrl_reg_eth>;
149 pinctrl-0 = <&pinctrl_usb1_vbus>;
[all …]
H A Dimx8mp-msc-sm2s.dtsi25 pinctrl-0 = <&pinctrl_usb0_vbus>;
36 pinctrl-0 = <&pinctrl_usb1_vbus>;
46 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
70 lcd0_backlight: backlight-0 {
73 pinctrl-0 = <&pinctrl_lcd0_backlight>;
74 pwms = <&pwm1 0 100000 0>;
75 brightness-levels = <0 255>;
85 pinctrl-0 = <&pinctrl_lcd1_backlight>;
86 pwms = <&pwm2 0 100000 0>;
87 brightness-levels = <0 255>;
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mm-emcon.dtsi19 pinctrl-0 = <&pinctrl_gpio_led>;
38 pwms = <&pwm1 0 50000 0>;
40 0 4 8 16 32 64 80 96 112
68 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
76 pinctrl-0 = <&pinctrl_fec1>;
84 #size-cells = <0>;
86 ethphy0: ethernet-phy@0 {
88 reg = <0>;
97 pinctrl-0
[all...]
H A Dimx8mp-icore-mx8mp-edimm2.2.dts28 pinctrl-0 = <&pinctrl_reg_usb1>;
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
49 pinctrl-0 = <&pinctrl_eqos>;
57 #size-cells = <0>;
61 micrel,led-mode = <0>;
70 pinctrl-0 = <&pinctrl_uart2>;
105 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
113 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
114 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
115 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx53-m53menlo.dts15 pinctrl-0 = <&pinctrl_power_button>;
27 pinctrl-0 = <&pinctrl_power_out>;
35 pinctrl-0 = <&pinctrl_led>;
61 #size-cells = <0>;
63 port@0 {
64 reg = <0>;
84 pinctrl-0 = <&pinctrl_display_gpio>;
86 enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
97 pinctrl-0 = <&pinctrl_beeper>;
106 gpio = <&gpio1 2 0>;
[all …]
H A Dimx53-smd.dts16 reg = <0x70000000 0x40000000>;
24 gpios = <&gpio2 14 0>;
30 gpios = <&gpio2 15 0>;
38 pinctrl-0 = <&pinctrl_esdhc1>;
46 pinctrl-0 = <&pinctrl_esdhc2>;
53 pinctrl-0 = <&pinctrl_uart3>;
60 pinctrl-0 = <&pinctrl_ecspi1>;
64 zigbee: mc1323@0 {
67 reg = <0>;
[all...]
H A Dimx53-cx9020.dts20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
24 display-0 {
26 #size-cells = <0>;
30 pinctrl-0 = <&pinctrl_ipu_disp0>;
32 port@0 {
33 reg = <0>;
66 #size-cells = <0>;
[all...]
H A Dimx53-sk-imx53.dts29 reg = <0x70000000 0x20000000>;
53 pinctrl-0 = <&pinctrl_audmux>;
59 pinctrl-0 = <&pinctrl_can1>;
75 pinctrl-0 = <&pinctrl_ecspi1>;
82 pinctrl-0 = <&pinctrl_ecspi2>;
91 pinctrl-0 = <&pinctrl_esdhc1>;
97 pinctrl-0 = <&pinctrl_fec>;
105 #size-cells = <0>;
107 phy0: ethernet-phy@0 {
108 reg = <0>;
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx53-qsrb.dts19 MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 /* IRQ */
29 pinctrl-0 = <&pinctrl_pmic>;
30 reg = <0x08>;
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_4xxxvf/
H A Dadf_4xxxvf_hw_data.h7 #define ADF_4XXXIOV_ACCELERATORS_MASK 0x1
8 #define ADF_4XXXIOV_ACCELENGINES_MASK 0x1
13 #define ADF_4XXXIOV_TX_RINGS_MASK 0x1
14 #define ADF_4XXXIOV_ETR_BAR 0
17 #define ADF_4XXXIOV_VINTSOU_OFFSET 0x0
18 #define ADF_4XXXIOV_VINTMSK_OFFSET 0x4
19 #define ADF_4XXXIOV_VINTSOUPF2VM_OFFSET 0x1000
20 #define ADF_4XXXIOV_VINTMSKPF2VM_OFFSET 0x1004
21 #define ADF_4XXX_DEF_ASYM_MASK 0x1
24 #define ADF_4XXXIOV_VFFUSECTL0_OFFSET (0x40)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,hdmi-phy-qmp.yaml52 const: 0
55 const: 0
71 reg = <0x009a0600 0x1c4>,
72 <0x009a0a00 0x124>,
73 <0x009a0c00 0x124>,
74 <0x009a0e00 0x124>,
75 <0x009a1000 0x124>,
76 <0x009a1200 0x0c8>;
90 #clock-cells = <0>;
91 #phy-cells = <0>;
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dmotorola-mapphone-common.dtsi15 reg = <0x80000000 0x3fd00000>; /* 1021 MB */
21 pinctrl-0 = <&poweroff_gpio>;
28 pinctrl-0 = <&hdmi_hpd_gpio>;
118 pinctrl-0 = <&dss_hdmi_pins>;
125 lanes = <1 0 3 2 5 4 7 6>;
133 reg = <0x48>;
134 pinctrl-0 = <&tmp105_irq>;
138 &omap4_pmx_core 0x14e>;
158 pinctrl-0
[all...]
H A Domap5-igep0050.dts16 reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */
25 pinctrl-0 = <&power_button_pin>;
39 gpios = <&tca6416 1 0>;
44 gpios = <&tca6416 2 0>;
49 gpios = <&tca6416 3 0>;
61 pinctrl-0 = <&i2c4_pins>;
65 reg = <0x21>;
90 OMAP5_IOPAD(0x0f8, PIN_INPUT | MUX_MODE0) /* i2c4_scl */
91 OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */
97 OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */
[all …]
H A Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Despressif11 # cfg_holder=4617=0x1209
12 0 uleshort 4617
13 # remaining settings normally 0x5A+offset XORed; free_1D5[20] empty since 5.12.0e
14 >0x1D5 ubequad 0x2f30313233343536 configuration of Tasmota firmware (ESP8266)
17 # version like 6.2.1.0 ~ 0x06020100 XORed to 0x63666262
18 >>11 ubyte^0x65 x \b, version %u
19 >>10 ubyte^0x64 x \b.%u
20 >>9 ubyte^0x63 x \b.%u
21 >>8 ubyte^0x62 x \b.%u
24 >>0x165 ubyte^0x1BF x \b, hostname %c
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4vf.c7 { "SGE_KDOORBELL", 0x000, 0 },
10 { "PIDX", 0, 14 },
11 { "SGE_GTS", 0x004, 0 },
15 { "CIDXInc", 0, 12 },
17 { NULL, 0, 0 }
21 { "SGE_VF_KDOORBELL", 0x000, 0 },
25 { "PIDX", 0, 13 },
26 { "SGE_VF_GTS", 0x004, 0 },
30 { "CIDXInc", 0, 12 },
32 { NULL, 0, 0 }
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]

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