Home
last modified time | relevance | path

Searched +full:0 +full:x1c19 (Results 1 – 25 of 28) sorted by relevance

12

/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
H A Ddcn_3_0_3_offset.h12 // base address: 0x0
13 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
14 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
15 …VGA_MEM_READ_PAGE_ADDR 0x0001
16 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
17 …VGA_RENDER_CONTROL 0x0000
19 …VGA_SEQUENCER_RESET_CONTROL 0x0001
21 …VGA_MODE_CONTROL 0x0002
23 …VGA_SURFACE_PITCH_SELECT 0x0003
25 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_2_0_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_3_2_1_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DSCCLK3_DTO_PARAM 0x0045
46 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
[all …]
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]
H A Ddcn_4_1_0_offset.h11 // base address: 0x0
12 …DENTIST_DISPCLK_CNTL 0x0064
17 // base address: 0x0
18 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
20 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
22 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
24 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
26 …DP_DTO_DBUF_EN 0x0044
28 …DSCCLK3_DTO_PARAM 0x0045
30 …DSCCLK4_DTO_PARAM 0x0046
[all …]
H A Ddcn_3_0_2_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_3_1_6_offset.h30 // base address: 0x1300000
31 …CONTROLLER0_GLOBAL_CAPABILITIES 0x4b7000
33 …CONTROLLER0_MINOR_VERSION 0x4b7000
35 …CONTROLLER0_MAJOR_VERSION 0x4b7000
37 …CONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b7001
39 …CONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b7001
41 …CONTROLLER0_GLOBAL_CONTROL 0x4b7002
43 …CONTROLLER0_WAKE_ENABLE 0x4b7003
45 …CONTROLLER0_STATE_CHANGE_STATUS 0x4b7003
47 …CONTROLLER0_GLOBAL_STATUS 0x4b7004
[all …]
H A Ddcn_3_1_4_offset.h31 // base address: 0x0
32 …AZCONTROLLER0_CORB_WRITE_POINTER 0x0000
33 …e regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 0
34 …AZCONTROLLER0_CORB_READ_POINTER 0x0000
35 …e regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 0
36 …AZCONTROLLER0_CORB_CONTROL 0x0001
37 …e regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 0
38 …AZCONTROLLER0_CORB_STATUS 0x0001
39 …e regAZCONTROLLER0_CORB_STATUS_BASE_IDX 0
40 …AZCONTROLLER0_CORB_SIZE 0x0001
[all …]
H A Ddcn_3_5_1_offset.h7 // base address: 0x1300000
8 …OBAL_CAPABILITIES 0x4b7000
10 …NOR_VERSION 0x4b7000
12 …JOR_VERSION 0x4b7000
14 …TPUT_PAYLOAD_CAPABILITY 0x4b7001
16 …PUT_PAYLOAD_CAPABILITY 0x4b7001
18 …OBAL_CONTROL 0x4b7002
20 …KE_ENABLE 0x4b7003
22 …ATE_CHANGE_STATUS 0x4b7003
24 …OBAL_STATUS 0x4b7004
[all …]
H A Ddcn_3_5_0_offset.h28 // base address: 0x1300000
29 …OBAL_CAPABILITIES 0x4b7000
31 …NOR_VERSION 0x4b7000
33 …JOR_VERSION 0x4b7000
35 …TPUT_PAYLOAD_CAPABILITY 0x4b7001
37 …PUT_PAYLOAD_CAPABILITY 0x4b7001
39 …OBAL_CONTROL 0x4b7002
41 …KE_ENABLE 0x4b7003
43 …ATE_CHANGE_STATUS 0x4b7003
45 …OBAL_STATUS 0x4b7004
[all …]
H A Ddcn_3_1_5_offset.h27 // base address: 0x0
28 …DENTIST_DISPCLK_CNTL 0x0064
33 // base address: 0x0
34 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
36 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
38 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
40 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
42 …DP_DTO_DBUF_EN 0x0044
44 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
46 …DCCG_GATE_DISABLE_CNTL4 0x0049
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/pci/
H A Dquirks.c93 * Return 0 if the link has been successfully retrained. Return an error
99 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
269 u8 cls = 0; in pci_apply_final_quirks()
303 return 0; in pci_apply_final_quirks()
341 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
345 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
391 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
392 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
395 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
397 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]

12