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12

/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Dr1001 r100 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr2001 r200 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/include/linux/mfd/mt6358/
H A Dregisters.h10 #define MT6358_SWCID 0xa
11 #define MT6358_TOPSTATUS 0x28
12 #define MT6358_TOP_RST_MISC 0x14c
13 #define MT6358_MISC_TOP_INT_CON0 0x188
14 #define MT6358_MISC_TOP_INT_STATUS0 0x194
15 #define MT6358_TOP_INT_STATUS0 0x19e
16 #define MT6358_SCK_TOP_INT_CON0 0x52e
17 #define MT6358_SCK_TOP_INT_STATUS0 0x53a
18 #define MT6358_EOSC_CALI_CON0 0x540
19 #define MT6358_EOSC_CALI_CON1 0x542
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/linux/include/linux/mfd/mt6359/
H A Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/linux/arch/mips/include/asm/
H A Dgt64120.h21 #define GT_CPU_OFS 0x000
23 #define GT_MULTI_OFS 0x120
26 #define GT_SCS10LD_OFS 0x008
27 #define GT_SCS10HD_OFS 0x010
28 #define GT_SCS32LD_OFS 0x018
29 #define GT_SCS32HD_OFS 0x020
30 #define GT_CS20LD_OFS 0x028
31 #define GT_CS20HD_OFS 0x030
32 #define GT_CS3BOOTLD_OFS 0x038
33 #define GT_CS3BOOTHD_OFS 0x040
[all …]
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_pa_pmu.c20 #define PA_PERF_CTRL 0x1c00
21 #define PA_EVENT_CTRL 0x1c04
22 #define PA_TT_CTRL 0x1c08
23 #define PA_TGTID_CTRL 0x1c14
24 #define PA_SRCID_CTRL 0x1c18
27 #define PA_INT_MASK 0x1c70
28 #define PA_INT_STATUS 0x1c78
29 #define PA_INT_CLEAR 0x1c7c
31 #define H60PA_INT_STATUS 0x1c70
32 #define H60PA_INT_MASK 0x1c74
[all …]
H A Dhisi_uncore_sllc_pmu.c20 #define SLLC_INT_MASK 0x0814
21 #define SLLC_INT_STATUS 0x0818
22 #define SLLC_INT_CLEAR 0x081c
23 #define SLLC_PERF_CTRL 0x1c00
24 #define SLLC_SRCID_CTRL 0x1c04
25 #define SLLC_TGTID_CTRL 0x1c08
26 #define SLLC_EVENT_CTRL 0x1c14
27 #define SLLC_EVENT_TYPE0 0x1c18
28 #define SLLC_VERSION 0x1cf0
29 #define SLLC_EVENT_CNT0_L 0x1d00
[all …]
/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h12 // base address: 0x0
13 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
14 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
15 …VGA_MEM_READ_PAGE_ADDR 0x0001
16 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
17 …VGA_RENDER_CONTROL 0x0000
19 …VGA_SEQUENCER_RESET_CONTROL 0x0001
21 …VGA_MODE_CONTROL 0x0002
23 …VGA_SURFACE_PITCH_SELECT 0x0003
25 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
/linux/drivers/pci/
H A Dquirks.c93 * Return 0 if the link has been successfully retrained. Return an error
99 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
269 u8 cls = 0; in pci_apply_final_quirks()
303 return 0; in pci_apply_final_quirks()
341 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
345 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
391 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
392 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
395 if (pm1a & 0x10) { in quirk_tigerpoint_bm_sts()
397 outw(0x10, pmbase); in quirk_tigerpoint_bm_sts()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c_table.c10 0x010, 0x00000043,
11 0x025, 0x0000001D,
12 0x026, 0x000000CE,
13 0x04F, 0x00000001,
14 0x029, 0x000000F9,
15 0x420, 0x00000080,
16 0x421, 0x0000001F,
17 0x428, 0x0000000A,
18 0x429, 0x00000010,
19 0x430, 0x00000000,
[all …]

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