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/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml136 enum: [0, 1]
303 reg = <0x18800000 0x800000>;
320 iommus = <&anoc2_smmu 0x1900>,
321 <&anoc2_smmu 0x1901>;
330 iommus = <&apps_smmu 0x1c02 0x1>;
340 reg = <0xa000000 0x200000>;
H A Dqcom,ath11k.yaml276 reg = <0xc000000 0x2000000>;
277 interrupts = <0 320 1>,
278 <0 319 1>,
279 <0 318 1>,
280 <0 317 1>,
281 <0 316 1>,
282 <0 315 1>,
283 <0 314 1>,
284 <0 311 1>,
285 <0 310 1>,
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
[all …]
H A Dccs-regs.h20 #define CCS_R_MODULE_MODEL_ID CCI_REG16(0x0000)
21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
24 #define CCS_PIXEL_ORDER_GRBG 0U
28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
29 #define CCS_MIPI_CCS_VERSION_V1_0 0x10
30 #define CCS_MIPI_CCS_VERSION_V1_1 0x11
32 #define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
33 #define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_ops.c26 0,
27 0,
28 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */
29 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */
30 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */
31 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */
32 0x1d02, /* win 6: addr=0x1d02000, size=4096 bytes */
33 0x1d80, /* win 7: addr=0x1d80000, size=4096 bytes */
34 0x1d81, /* win 8: addr=0x1d81000, size=4096 bytes */
35 0x1d82, /* win 9: addr=0x1d82000, size=4096 bytes */
[all …]
/linux/sound/hda/codecs/realtek/
H A Drealtek.c15 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in coef_mutex_lock()
16 val = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_PROC_COEF, 0); in coef_mutex_lock()
31 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_COEF_INDEX, coef_idx); in __alc_read_coefex_idx()
32 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_PROC_COEF, coef_val); in __alc_read_coefex_idx()
63 /* a special bypass for COEF 0; read the cached value at the second time */ in alc_write_coefex_idx()
69 spec->coef0 = alc_read_coef_idx(codec, 0); in __alc_update_coefex_idx()
106 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, in alc_process_coef_fw()
133 snd_hda_codec_write(codec, codec->core.afg, 0, in alc_write_gpio_data()
[all...]
H A Dalc662.c28 static const hda_nid_t alc662_ignore[] = { 0x1d, 0 }; in alc662_parse_auto_config()
29 static const hda_nid_t alc663_ssids[] = { 0x15, 0x1b, 0x14, 0x21 }; in alc662_parse_auto_config()
30 static const hda_nid_t alc662_ssids[] = { 0x15, 0x1b, 0x14, 0 }; in alc662_parse_auto_config()
33 if (codec->core.vendor_id == 0x10ec0272 || codec->core.vendor_id == 0x10ec0663 || in alc662_parse_auto_config()
34 codec->core.vendor_id == 0x10ec0665 || codec->core.vendor_id == 0x10ec0670 || in alc662_parse_auto_config()
35 codec->core.vendor_id == 0x10ec0671) in alc662_parse_auto_config()
47 if (snd_hda_override_amp_caps(codec, 0x2, HDA_OUTPUT, in alc272_fixup_mario()
48 (0x3b << AC_AMPCAP_OFFSET_SHIFT) | in alc272_fixup_mario()
49 (0x3b << AC_AMPCAP_NUM_STEPS_SHIFT) | in alc272_fixup_mario()
50 (0x03 << AC_AMPCAP_STEP_SIZE_SHIFT) | in alc272_fixup_mario()
[all …]
/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/linux/drivers/ata/
H A Dahci.c40 AHCI_PCI_BAR_STA2X11 = 0,
41 AHCI_PCI_BAR_CAVIUM = 0,
42 AHCI_PCI_BAR_LOONGSON = 0,
272 { PCI_VDEVICE(INTEL, 0x06d6), board_ahci_pcs_quirk }, /* Comet Lake PCH-H RAID */
273 { PCI_VDEVICE(INTEL, 0x2652), board_ahci_pcs_quirk }, /* ICH6 */
274 { PCI_VDEVICE(INTEL, 0x2653), board_ahci_pcs_quirk }, /* ICH6M */
275 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci_pcs_quirk }, /* ICH7 */
276 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci_pcs_quirk }, /* ICH7M */
277 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci_pcs_quirk }, /* ICH7R */
278 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
H A Ddcn_3_0_3_offset.h12 // base address: 0x0
13 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
14 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
15 …VGA_MEM_READ_PAGE_ADDR 0x0001
16 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
17 …VGA_RENDER_CONTROL 0x0000
19 …VGA_SEQUENCER_RESET_CONTROL 0x0001
21 …VGA_MODE_CONTROL 0x0002
23 …VGA_SURFACE_PITCH_SELECT 0x0003
25 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_1_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A Duncore-interconnect.json4 "Counter": "0,1",
5 "EventCode": "0x0F",
10 "UMask": "0x1",
15 "Counter": "0,1",
16 "EventCode": "0x0F",
21 "UMask": "0x2",
26 "Counter": "0,1",
27 "EventCode": "0x0f",
31 "UMask": "0x4",
36 "Counter": "0,1",
[all …]

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