| /linux/arch/powerpc/boot/dts/ | 
| H A D | ep88xc.dts | 19 		#size-cells = <0>;21 		PowerPC,885@0 {
 23 			reg = <0x0>;
 28 			timebase-frequency = <0>;
 29 			bus-frequency = <0>;
 30 			clock-frequency = <0>;
 38 		reg = <0x0 0x0>;
 45 		reg = <0xfa200100 0x40>;
 48 			0x0 0x0 0xfc000000 0x4000000
 49 			0x3 0x0 0xfa000000 0x1000000
 [all …]
 
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| /linux/drivers/hwtracing/intel_th/ | 
| H A D | pti.h | 12 	REG_PTI_CTL	= 0x1c00,15 #define PTI_EN		BIT(0)
 17 #define PTI_MODE	0xf0
 20 #define PTI_CLKDIV	0x000f0000
 21 #define PTI_PATGENMODE	0x00f00000
 26 #define LPP_DEST_PTI	BIT(0)
 
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| /linux/drivers/bus/ | 
| H A D | omap_l3_smx.h | 14 #define L3_COMPONENT			0x00015 #define L3_CORE				0x018
 16 #define L3_AGENT_CONTROL		0x020
 17 #define L3_AGENT_STATUS			0x028
 18 #define L3_ERROR_LOG			0x058
 23 #define L3_ERROR_LOG_ADDR		0x060
 26 #define L3_SI_CONTROL			0x020
 27 #define L3_SI_FLAG_STATUS_0		0x510
 31 #define L3_STATUS_0_MPUIA_BRST		(shift << 0)
 95 #define L3_SI_FLAG_STATUS_1		0x530
 [all …]
 
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| /linux/arch/arm/mach-omap2/ | 
| H A D | prm54xx.h | 24 #define OMAP54XX_PRM_BASE		0x4ae0600031 #define OMAP54XX_PRM_OCP_SOCKET_INST	0x0000
 32 #define OMAP54XX_PRM_CKGEN_INST		0x0100
 33 #define OMAP54XX_PRM_MPU_INST		0x0300
 34 #define OMAP54XX_PRM_DSP_INST		0x0400
 35 #define OMAP54XX_PRM_ABE_INST		0x0500
 36 #define OMAP54XX_PRM_COREAON_INST	0x0600
 37 #define OMAP54XX_PRM_CORE_INST		0x0700
 38 #define OMAP54XX_PRM_IVA_INST		0x1200
 39 #define OMAP54XX_PRM_CAM_INST		0x1300
 [all …]
 
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| H A D | prm7xx.h | 26 #define DRA7XX_PRM_BASE		0x4ae0600033 #define DRA7XX_PRM_OCP_SOCKET_INST	0x0000
 34 #define DRA7XX_PRM_CKGEN_INST		0x0100
 35 #define DRA7XX_PRM_MPU_INST		0x0300
 36 #define DRA7XX_PRM_DSP1_INST		0x0400
 37 #define DRA7XX_PRM_IPU_INST		0x0500
 38 #define DRA7XX_PRM_COREAON_INST		0x0628
 39 #define DRA7XX_PRM_CORE_INST		0x0700
 40 #define DRA7XX_PRM_IVA_INST		0x0f00
 41 #define DRA7XX_PRM_CAM_INST		0x1000
 [all …]
 
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| /linux/Documentation/devicetree/bindings/fsi/ | 
| H A D | ibm,fsi2spi.yaml | 30     const: 033   "^spi@[0-9a-f]+$":
 47         reg = <0x1c00 0x400>;
 49         #size-cells = <0>;
 51         spi@0 {
 53             reg = <0>;
 55             #size-cells = <0>;
 57             eeprom@0 {
 59                 reg = <0>;
 62                 size = <0x80000>;
 
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| /linux/sound/pci/ctxfi/ | 
| H A D | ctmixer.h | 20 #define INIT_VOL	0x1c00
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| /linux/Documentation/devicetree/bindings/iommu/ | 
| H A D | qcom,tbu.yaml | 62         reg = <0x150e1000 0x1000>;67         qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
 
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| /linux/drivers/edac/ | 
| H A D | altera_edac.h | 15 #define CV_CTLCFG_OFST             0x0018 #define CV_CTLCFG_ECC_EN           0x400
 19 #define CV_CTLCFG_ECC_CORR_EN      0x800
 20 #define CV_CTLCFG_GEN_SB_ERR       0x2000
 21 #define CV_CTLCFG_GEN_DB_ERR       0x4000
 26 #define CV_DRAMADDRW_OFST          0x2C
 29 #define DRAMADDRW_COLBIT_MASK      0x001F
 30 #define DRAMADDRW_COLBIT_SHIFT     0
 31 #define DRAMADDRW_ROWBIT_MASK      0x03E0
 33 #define CV_DRAMADDRW_BANKBIT_MASK  0x1C00
 [all …]
 
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| /linux/drivers/mfd/ | 
| H A D | timberdale.h | 23 #define TIMB_REV_MAJOR	0x0024 #define TIMB_REV_MINOR	0x04
 25 #define TIMB_HW_CONFIG	0x08
 26 #define TIMB_SW_RST	0x40
 29 #define TIMB_HW_CONFIG_SPI_8BIT	0x80
 31 #define TIMB_HW_VER_MASK	0x0f
 32 #define TIMB_HW_VER0		0x00
 33 #define TIMB_HW_VER1		0x01
 34 #define TIMB_HW_VER2		0x02
 35 #define TIMB_HW_VER3		0x03
 [all …]
 
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ | 
| H A D | tonga_baco.c | 40 	{ CMD_WRITE, mmGPIOPAD_EN, 0, 0, 0, 0x0 },41 	{ CMD_WRITE, mmGPIOPAD_PD_EN, 0, 0, 0, 0x0 },
 42 	{ CMD_WRITE, mmGPIOPAD_PU_EN, 0, 0, 0, 0x0 },
 43 	{ CMD_WRITE, mmGPIOPAD_MASK, 0, 0, 0, 0xff77ffff },
 44 	{ CMD_WRITE, mmDC_GPIO_DVODATA_EN, 0, 0, 0, 0x0 },
 45 	{ CMD_WRITE, mmDC_GPIO_DVODATA_MASK, 0, 0, 0, 0xffffffff },
 46 	{ CMD_WRITE, mmDC_GPIO_GENERIC_EN, 0, 0, 0, 0x0 },
 47 	{ CMD_READMODIFYWRITE, mmDC_GPIO_GENERIC_MASK, 0, 0, 0, 0x03333333 },
 48 	{ CMD_WRITE, mmDC_GPIO_SYNCA_EN, 0, 0, 0, 0x0 },
 49 	{ CMD_READMODIFYWRITE, mmDC_GPIO_SYNCA_MASK, 0, 0, 0, 0x00001111 }
 [all …]
 
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| /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ | 
| H A D | dcore0_tpc0_eml_spmu_regs.h | 23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x100025 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
 27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
 29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
 31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
 33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
 35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
 37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
 39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
 41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
 [all …]
 
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| /linux/include/linux/irqchip/ | 
| H A D | riscv-aplic.h | 14 #define APLIC_DOMAINCFG			0x000015 #define APLIC_DOMAINCFG_RDONLY		0x80000000
 18 #define APLIC_DOMAINCFG_BE		BIT(0)
 20 #define APLIC_SOURCECFG_BASE		0x0004
 22 #define APLIC_SOURCECFG_CHILDIDX_MASK	0x000003ff
 23 #define APLIC_SOURCECFG_SM_MASK	0x00000007
 24 #define APLIC_SOURCECFG_SM_INACTIVE	0x0
 25 #define APLIC_SOURCECFG_SM_DETACH	0x1
 26 #define APLIC_SOURCECFG_SM_EDGE_RISE	0x4
 27 #define APLIC_SOURCECFG_SM_EDGE_FALL	0x5
 [all …]
 
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| /linux/include/linux/mfd/wm8350/ | 
| H A D | supply.h | 17 #define WM8350_BATTERY_CHARGER_CONTROL_1        0xA818 #define WM8350_BATTERY_CHARGER_CONTROL_2        0xA9
 19 #define WM8350_BATTERY_CHARGER_CONTROL_3        0xAA
 22  * R168 (0xA8) - Battery Charger Control 1
 24 #define WM8350_CHG_ENA_R168                     0x8000
 25 #define WM8350_CHG_THR                          0x2000
 26 #define WM8350_CHG_EOC_SEL_MASK                 0x1C00
 27 #define WM8350_CHG_TRICKLE_TEMP_CHOKE           0x0200
 28 #define WM8350_CHG_TRICKLE_USB_CHOKE            0x0100
 29 #define WM8350_CHG_RECOVER_T                    0x0080
 [all …]
 
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| /linux/include/sound/ | 
| H A D | cs48l32_registers.h | 13 #define CS48L32_DEVID				0x014 #define CS48L32_REVID				0x4
 15 #define CS48L32_OTPID				0x10
 16 #define CS48L32_SFT_RESET			0x20
 17 #define CS48L32_CTRL_IF_DEBUG3			0xA8
 18 #define CS48L32_MCU_CTRL1			0x804
 19 #define CS48L32_GPIO1_CTRL1			0xc08
 20 #define CS48L32_GPIO3_CTRL1			0xc10
 21 #define CS48L32_GPIO7_CTRL1			0xc20
 22 #define CS48L32_GPIO16_CTRL1			0xc44
 [all …]
 
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| /linux/drivers/video/fbdev/ | 
| H A D | sm712.h | 23 #define dac_reg	(0x3c8)24 #define dac_val	(0x3c9)
 31 #define SIZE_SR00_SR04      (0x04 - 0x00 + 1)
 32 #define SIZE_SR10_SR24      (0x24 - 0x10 + 1)
 33 #define SIZE_SR30_SR75      (0x75 - 0x30 + 1)
 34 #define SIZE_SR80_SR93      (0x93 - 0x80 + 1)
 35 #define SIZE_SRA0_SRAF      (0xAF - 0xA0 + 1)
 36 #define SIZE_GR00_GR08      (0x08 - 0x00 + 1)
 37 #define SIZE_AR00_AR14      (0x14 - 0x00 + 1)
 38 #define SIZE_CR00_CR18      (0x18 - 0x00 + 1)
 [all …]
 
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| /linux/sound/hda/codecs/helpers/ | 
| H A D | hp_x360.c | 10 		{ 0x17, 0x90170110 },  in alc295_fixup_hp_top_speakers()14 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0000), WRITE_COEF(0x28, 0x0000), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 15 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x003f), WRITE_COEF(0x28, 0x1000), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 16 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0004), WRITE_COEF(0x28, 0x0600), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 17 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x0006), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 18 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0xc0c0), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 19 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0008), WRITE_COEF(0x28, 0xb000), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 20 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x002e), WRITE_COEF(0x28, 0x0800), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 21 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x00c1), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 22 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0x0320), WRITE_COEF(0x29, 0xb…  in alc295_fixup_hp_top_speakers()
 [all …]
 
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| /linux/drivers/net/wireless/broadcom/b43/ | 
| H A D | wa.c | 24 	b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);  in b43_wa_initgains()25 	b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F);  in b43_wa_initgains()
 27 		b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);  in b43_wa_initgains()
 28 	b43_radio_write16(dev, 0x0002, 0x1FBF);  in b43_wa_initgains()
 30 	b43_phy_write(dev, 0x0024, 0x4680);  in b43_wa_initgains()
 31 	b43_phy_write(dev, 0x0020, 0x0003);  in b43_wa_initgains()
 32 	b43_phy_write(dev, 0x001D, 0x0F40);  in b43_wa_initgains()
 33 	b43_phy_write(dev, 0x001F, 0x1C00);  in b43_wa_initgains()
 35 		b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400);  in b43_wa_initgains()
 37 		b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00);  in b43_wa_initgains()
 [all …]
 
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| /linux/include/video/ | 
| H A D | neomagic.h | 11 #define NEO_BS0_BLT_BUSY        0x0000000112 #define NEO_BS0_FIFO_AVAIL      0x00000002
 13 #define NEO_BS0_FIFO_PEND       0x00000004
 15 #define NEO_BC0_DST_Y_DEC       0x00000001
 16 #define NEO_BC0_X_DEC           0x00000002
 17 #define NEO_BC0_SRC_TRANS       0x00000004
 18 #define NEO_BC0_SRC_IS_FG       0x00000008
 19 #define NEO_BC0_SRC_Y_DEC       0x00000010
 20 #define NEO_BC0_FILL_PAT        0x00000020
 21 #define NEO_BC0_SRC_MONO        0x00000040
 [all …]
 
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| /linux/arch/sh/boards/ | 
| H A D | board-polaris.c | 23 #define BCR2		(0xFFFFFF62)24 #define WCR2		(0xFFFFFF66)
 25 #define AREA5_WAIT_CTRL	(0x1C00)
 26 #define WAIT_STATES_10	(0x7)
 30 	REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
 31 	REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
 35 	[0] = {
 38 		.end		= PA_EXT5 + 0x1fff,
 58 	.id		= 0,
 66 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
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| /linux/drivers/staging/gpib/uapi/ | 
| H A D | gpib.h | 11 #define GPIB_MAX_NUM_DESCRIPTORS 0x100014 	DCAS_NUM = 0,
 59 	EOS_MASK = 0x1c00,
 60 	REOS = 0x0400,		/* Terminate reads on EOS	*/
 61 	XEOS = 0x800,	/* assert EOI when EOS char is sent */
 62 	BIN = 0x1000		/* Do 8-bit compare on EOS	*/
 67 	VALID_DAV = 0x01,
 68 	VALID_NDAC = 0x02,
 69 	VALID_NRFD = 0x04,
 70 	VALID_IFC = 0x08,
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| /linux/Documentation/devicetree/bindings/pci/ | 
| H A D | qcom,pcie-sm8350.yaml | 94             reg = <0 0x01c00000 0 0x3000>,95                   <0 0x60000000 0 0xf1d>,
 96                   <0 0x60000f20 0 0xa8>,
 97                   <0 0x60001000 0 0x1000>,
 98                   <0 0x60100000 0 0x100000>;
 100             ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
 101                      <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
 103             bus-range = <0x00 0xff>;
 105             linux,pci-domain = <0>;
 142             interrupt-map-mask = <0 0 0 0x7>;
 [all …]
 
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| H A D | qcom,pcie-sm8250.yaml | 104             reg = <0 0x01c00000 0 0x3000>,105                   <0 0x60000000 0 0xf1d>,
 106                   <0 0x60000f20 0 0xa8>,
 107                   <0 0x60001000 0 0x1000>,
 108                   <0 0x60100000 0 0x100000>,
 109                   <0 0x01c03000 0 0x1000>;
 111             ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
 112                      <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
 114             bus-range = <0x00 0xff>;
 116             linux,pci-domain = <0>;
 [all …]
 
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| /linux/drivers/net/ethernet/intel/idpf/ | 
| H A D | idpf_lan_vf_regs.h | 8 #define VFGEN_RSTAT			0x000088009 #define VFGEN_RSTAT_VFR_STATE_S		0
 10 #define VFGEN_RSTAT_VFR_STATE_M		GENMASK(1, 0)
 13 #define VF_BASE				0x00006000
 15 #define VF_ATQBAL			(VF_BASE + 0x1C00)
 16 #define VF_ATQBAH			(VF_BASE + 0x1800)
 17 #define VF_ATQLEN			(VF_BASE + 0x0800)
 18 #define VF_ATQLEN_ATQLEN_S		0
 19 #define VF_ATQLEN_ATQLEN_M		GENMASK(9, 0)
 28 #define VF_ATQH				(VF_BASE + 0x0400)
 [all …]
 
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| /linux/include/linux/platform_data/x86/ | 
| H A D | pmc_atom.h | 13 #define	PCI_DEVICE_ID_VLV_PMC	0x0F1C15 #define	PCI_DEVICE_ID_CHT_PMC	0x229C
 18 #define	PMC_BASE_ADDR_OFFSET	0x44
 19 #define	PMC_BASE_ADDR_MASK	0xFFFFFE00
 20 #define	PMC_MMIO_REG_LEN	0x100
 24 #define	PMC_FUNC_DIS		0x34
 25 #define	PMC_FUNC_DIS_2		0x38
 32 #define	PMC_S0IX_WAKE_EN	0x3C
 47 #define PMC_CLK_CTL_OFFSET		0x60
 50 #define PMC_CLK_CTL_GATED_ON_D3		0x0
 [all …]
 
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