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/freebsd/usr.sbin/bhyve/amd64/
H A Dpci_gvt-d-opregion.h41 /// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to
43 /// Offset 0x0, Size 0x100
46 int8_t sign[0x10]; ///< Offset 0x00 OpRegion Signature
47 uint32_t size; ///< Offset 0x10 OpRegion Size
48 uint32_t over; ///< Offset 0x14 OpRegion Structure Version
49 uint8_t sver[0x20]; ///< Offset 0x18 System BIOS Build Version
50 uint8_t vver[0x10]; ///< Offset 0x38 Video BIOS Build Version
51 uint8_t gver[0x10]; ///< Offset 0x48 Graphic Driver Build Version
52 uint32_t mbox; ///< Offset 0x58 Supported Mailboxes
53 uint32_t dmod; ///< Offset 0x5C Driver Model
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Drpmh-rsc.txt52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92 register offsets for DRV2 start at 0D00, the register calculations are like
94 DRV0: 0x179C0000
95 DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96 DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97 TCS-OFFSET: 0xD00
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
[all …]
H A Dqcom,rpmh-rsc.yaml78 enum: [ 0, 1, 2, 3 ]
97 - const: drv-0
115 '^regulators(-[0-9])?$':
133 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
134 // 2, the register offsets for DRV2 start at 0D00, the register
136 // DRV0: 0x179C0000
137 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
138 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
139 // TCS-OFFSET: 0xD00
145 reg = <0x179c0000 0x10000>,
[all …]
/freebsd/sys/dev/agp/
H A Dagpreg.h35 #define AGP_APBASE PCIR_BAR(0)
40 #define AGP_CAPID 0x0
41 #define AGP_STATUS 0x4
42 #define AGP_COMMAND 0x8
43 #define AGP_STATUS_AGP3 0x0008
44 #define AGP_STATUS_RQ_MASK 0xff000000
45 #define AGP_COMMAND_RQ_MASK 0xff000000
46 #define AGP_STATUS_ARQSZ_MASK 0xe000
47 #define AGP_COMMAND_ARQSZ_MASK 0xe000
48 #define AGP_STATUS_CAL_MASK 0x1c00
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
H A Dadder875-redboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xfa200100 0x40>;
54 0 0 0xfe000000 0x00800000
55 2 0 0xfa100000 0x00008000
[all …]
H A Dadder875-uboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xff000100 0x40>;
54 0 0 0xfe000000 0x01000000
57 flash@0,0 {
[all …]
H A Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]
H A Dmpc885ads.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xff000100 0x40>;
48 0x0 0x0 0xfe000000 0x800000
49 0x1 0x0 0xff080000 0x8000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/fsi/
H A Dibm,fsi2spi.yaml30 const: 0
33 "^spi@[0-9a-f]+$":
47 reg = <0x1c00 0x400>;
49 #size-cells = <0>;
51 spi@0 {
53 reg = <0>;
55 #size-cells = <0>;
57 eeprom@0 {
59 reg = <0>;
62 size = <0x80000>;
/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,tbu.yaml62 reg = <0x150e1000 0x1000>;
67 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>;
/freebsd/sys/powerpc/powermac/
H A Dviareg.h32 #define vBufB 0x0000 /* register B */
33 #define vDirB 0x0400 /* data direction register */
34 #define vDirA 0x0600 /* data direction register */
35 #define vT1C 0x0800 /* Timer 1 counter Lo */
36 #define vT1CH 0x0a00 /* Timer 1 counter Hi */
37 #define vSR 0x1400 /* shift register */
38 #define vACR 0x1600 /* aux control register */
39 #define vPCR 0x1800 /* peripheral control register */
40 #define vIFR 0x1a00 /* interrupt flag register */
41 #define vIER 0x1c00 /* interrupt enable register */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Dibm-power10-dual.dtsi8 #size-cells = <0>;
10 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
12 cfam@0,0 {
13 reg = <0 0>;
16 chip-id = <0>;
20 reg = <0x1000 0x400>;
25 reg = <0x1800 0x400>;
27 #size-cells = <0>;
29 cfam0_i2c0: i2c-bus@0 {
31 #size-cells = <0>;
[all …]
H A Dibm-power11-quad.dtsi126 #size-cells = <0>;
129 cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
131 cfam@0,0 {
132 reg = <0 0>;
135 chip-id = <0>;
139 reg = <0x1000 0x400>;
144 reg = <0x1800 0x400>;
146 #size-cells = <0>;
148 cfam0_i2c0: i2c-bus@0 {
149 reg = <0>; /* OMI01 */
[all …]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_udma_iofic_regs.h54 uint32_t rsrvd1[(0x1c00) >> 2];
/freebsd/sys/dev/etherswitch/felix/
H A Dfelix_reg.h34 #define FELIX_MDIO_BASE 0x1C00
36 #define FELIX_DEVCPU_GCB_RST 0x70004
37 #define FELIX_DEVCPU_GCB_RST_EN BIT(0)
39 #define FELIX_ANA_VT 0x287F34
41 #define FELIX_ANA_VT_PORTMASK_MASK 0x7F
42 #define FELIX_ANA_VT_STS (BIT(0) | BIT(1))
43 #define FELIX_ANA_VT_RESET (BIT(0) | BIT(1))
45 #define FELIX_ANA_VT_READ BIT(0)
46 #define FELIX_ANA_VT_IDLE 0
47 #define FELIX_ANA_VTIDX 0x287F38
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie-sm8350.yaml92 reg = <0 0x01c00000 0 0x3000>,
93 <0 0x60000000 0 0xf1d>,
94 <0 0x60000f20 0 0xa8>,
95 <0 0x60001000 0 0x1000>,
96 <0 0x60100000 0 0x100000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
99 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
139 interrupt-map-mask = <0 0 0 0x7>;
[all …]
H A Dqcom,pcie-sm8250.yaml102 reg = <0 0x01c00000 0 0x3000>,
103 <0 0x60000000 0 0xf1d>,
104 <0 0x60000f20 0 0xa8>,
105 <0 0x60001000 0 0x1000>,
106 <0 0x60100000 0 0x100000>,
107 <0 0x01c03000 0 0x1000>;
109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
[all …]
H A Dqcom,pcie-sm8450.yaml103 reg = <0 0x01c00000 0 0x3000>,
104 <0 0x60000000 0 0xf1d>,
105 <0 0x60000f20 0 0xa8>,
106 <0 0x60001000 0 0x1000>,
107 <0 0x60100000 0 0x100000>;
109 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
112 bus-range = <0x00 0xff>;
114 linux,pci-domain = <0>;
158 interrupt-map-mask = <0 0 0 0x7>;
[all …]
/freebsd/sys/dev/siis/
H A Dsiis.h30 #define ATA_DATA 0 /* (RW) data */
33 #define ATA_F_DMA 0x01 /* enable DMA */
34 #define ATA_F_OVL 0x02 /* enable overlap */
42 #define ATA_D_LBA 0x40 /* use LBA addressing */
43 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
48 #define ATA_E_ILI 0x01 /* illegal length */
49 #define ATA_E_NM 0x02 /* no media */
50 #define ATA_E_ABORT 0x04 /* command aborted */
51 #define ATA_E_MCR 0x08 /* media change request */
52 #define ATA_E_IDNF 0x10 /* ID not found */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-tphy.txt5 controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA.
23 the child's base address to 0, the physical address
72 reg = <0 0x11290000 0 0x800>;
78 reg = <0 0x11290800 0 0x100>;
85 reg = <0 0x11290800 0 0x700>;
92 reg = <0 0x11291000 0 0x100>;
113 phy-names = "usb2-0", "usb3-0";
122 shared 0x0000 SPLLC
123 0x0100 FMREG
124 u2 port0 0x0800 U2PHY_COM
[all …]
/freebsd/sys/contrib/device-tree/src/arm/sigmastar/
H A Dmstar-v7.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0x0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
80 ranges = <0x16001000 0x16001000 0x00007000>,
81 <0x1f000000 0x1f000000 0x00400000>,
82 <0xa0000000 0xa0000000 0x20000>;
86 reg = <0x16001000 0x1000>,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Dqcom,x1e80100-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^phy@[0-9a-f]+$":
74 reg = <0x0ae00000 0x1000>;
77 interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>,
78 <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>,
79 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>;
95 iommus = <&apps_smmu 0x1c00 0x2>;
103 reg = <0x0ae01000 0x8f000>,
104 <0x0aeb0000 0x2008>;
[all …]
H A Dqcom,sm8650-mdss.yaml38 "^display-controller@[0-9a-f]+$":
45 "^displayport-controller@[0-9a-f]+$":
52 "^dsi@[0-9a-f]+$":
61 "^phy@[0-9a-f]+$":
81 reg = <0x0ae00000 0x1000>;
97 iommus = <&apps_smmu 0x1c00 0x2>;
105 reg = <0x0ae01000 0x8f000>,
106 <0x0aeb0000 0x2008>;
127 interrupts = <0>;
131 #size-cells = <0>;
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DSPARCV9.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
44 defaultMaxPageSize = 0x100000; in SPARCV9()
45 defaultImageBase = 0x100000; in SPARCV9()
105 write32be(loc, (read32be(loc) & ~0x3fffffff) | ((val >> 2) & 0x3fffffff)); in relocate()
110 write32be(loc, (read32be(loc) & ~0x003fffff) | (val & 0x003fffff)); in relocate()
116 write32be(loc, (read32be(loc) & ~0x003fffff) | ((val >> 10) & 0x003fffff)); in relocate()
121 write32be(loc, (read32be(loc) & ~0x003fffff) | ((val >> 10) & 0x003fffff)); in relocate()
126 write32be(loc, (read32be(loc) & ~0x0007ffff) | ((val >> 2) & 0x0007ffff)); in relocate()
131 write32be(loc, (read32be(loc) & ~0x000003ff) | (val & 0x000003ff)); in relocate()
135 write32be(loc, (read32be(loc) & ~0x00001fff) | (val & 0x000003ff)); in relocate()
[all …]

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