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/linux/lib/fonts/
H A Dfont_ter16x32.c8 { 0, 0, FONTDATAMAX, 0 }, {
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x7f, 0xfc, 0x7f, 0xfc,
11 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
12 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
13 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
14 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c, 0x70, 0x1c,
15 0x7f, 0xfc, 0x7f, 0xfc, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0 */
17 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/linux/drivers/mtd/spi-nor/
H A Deon.c13 .id = SNOR_ID(0x1c, 0x20, 0x16),
17 .id = SNOR_ID(0x1c, 0x20, 0x17),
21 .id = SNOR_ID(0x1c, 0x30, 0x14),
26 .id = SNOR_ID(0x1c, 0x30, 0x16),
30 .id = SNOR_ID(0x1c, 0x30, 0x17),
35 .id = SNOR_ID(0x1c, 0x31, 0x16),
41 .id = SNOR_ID(0x1c, 0x38, 0x17),
45 .id = SNOR_ID(0x1c, 0x70, 0x15),
50 .id = SNOR_ID(0x1c, 0x70, 0x16),
54 .id = SNOR_ID(0x1c, 0x70, 0x17),
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h27 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
28 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
29 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
30 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
31 …_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
32 …_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
33 …_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
34 …_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
36 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
37 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
[all …]
H A Ddcn_3_0_2_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_3_0_0_sh_mask.h8 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
9 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
10 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
11 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
13 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
14 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
15 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
16 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
18 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
19 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_2_0_0_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_3_1_4_sh_mask.h31 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
32 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
34 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
35 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
36 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
37 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
39 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
40 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
41 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
42 …LLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
[all …]
H A Ddcn_3_0_1_sh_mask.h27 …_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
28 …_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
29 …_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
30 …_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
31 …_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
32 …ABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L
33 …ABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L
34 …ABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L
35 …ABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L
36 …ABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L
[all …]
H A Ddcn_3_1_2_sh_mask.h27 …ROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
28 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
29 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
30 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
31 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
32 …ER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L
33 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L
34 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L
35 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L
36 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L
[all …]
H A Ddcn_3_1_5_sh_mask.h27 …T_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
28 …T_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
29 …T_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
30 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
31 …_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
32 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
33 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
34 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15
35 …_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16
36 …_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
[all …]
H A Ddcn_3_5_1_sh_mask.h6 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
7 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
8 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
9 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
10 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
11 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
12 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
13 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
14 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
15 …LLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
[all …]
H A Ddcn_3_5_0_sh_mask.h27 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
28 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
29 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
30 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
31 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
32 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
33 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
34 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
35 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
36 …LLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
[all …]
H A Ddcn_2_1_0_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
38 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
39 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_3_2_1_sh_mask.h27 …T_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0
28 …T_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8
29 …T_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf
30 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11
31 …_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12
32 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13
33 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14
34 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15
35 …_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16
36 …_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18
[all …]
H A Ddcn_3_1_6_sh_mask.h31 …ROLLER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
32 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
33 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
34 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
35 …ROLLER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
36 …ER0_GLOBAL_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L
37 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L
38 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L
39 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L
40 …ER0_GLOBAL_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L
[all …]
H A Ddcn_3_0_3_sh_mask.h14 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
15 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
16 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
17 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
19 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
20 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
21 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
22 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
24 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
25 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
/linux/drivers/video/fbdev/via/
H A Dhw.c13 {19, 19, 4, 0},
14 {26, 102, 5, 0},
15 {53, 112, 6, 0},
16 {41, 100, 7, 0},
17 {83, 108, 8, 0},
18 {87, 118, 9, 0},
19 {95, 115, 12, 0},
20 {108, 108, 13, 0},
21 {83, 83, 17, 0},
22 {67, 98, 20, 0},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vpe/
H A Dvpe_6_1_0_sh_mask.h29 …EC_START__START__SHIFT 0x0
30 …__START_MASK 0xFFFFFFFFL
32 …CODE_ADDR__VALUE__SHIFT 0x0
33 …CODE_ADDR__THID__SHIFT 0xf
34 …R__VALUE_MASK 0x00001FFFL
35 …R__THID_MASK 0x00008000L
37 …CODE_DATA__VALUE__SHIFT 0x0
38 …A__VALUE_MASK 0xFFFFFFFFL
40 …32_CNTL__HALT__SHIFT 0x0
41 …32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
/linux/arch/mips/include/asm/
H A Dcacheops.h18 #define CacheOp_Cache 0x03
19 #define CacheOp_Op 0x1c
21 #define Cache_I 0x00
22 #define Cache_D 0x01
23 #define Cache_T 0x02
24 #define Cache_V 0x02 /* Loongson-3 */
25 #define Cache_S 0x03
27 #define Index_Writeback_Inv 0x00
28 #define Index_Load_Tag 0x04
29 #define Index_Store_Tag 0x08
[all …]
/linux/crypto/
H A Dtestmgr.h33 * @ksize: Length of @key in bytes (0 if no key)
103 * @crypt_error: When @novrfy=0, the expected error from encrypt(). When
222 "\x63\x1c\xcd\x7b\xe1\x7e\xe4\xde\xc9\xa8\x89\xa1\x74\xcb\x3c\x63"
249 "\xC9\x7F\xF3\xAD\x59\x50\xAC\xCF\xBC\x11\x1C\x76\xF1\xA9\x52\x94"
252 "\xAF\x94\x28\xC2\xB7\xB8\x88\x3F\xE4\x46\x3A\x4B\xC8\x5B\x1C\xB3"
273 "\x61\xAD\xBD\x3A\x8A\x7E\x99\x1C\x5C\x05\x56\xA9\x4C\x31\x46\xA7"
371 "\x21\x79\x6D\xF9\xE9\x04\x6A\xE8\x32\xFF\xAE\xFD\x1C\x7B\x8C\x29"
376 "\x0D\x8B\x6C\x6D\x13\x74\xD5\x1C\xDE\xA9\xF4\x60\x37\xFE\x68\x77"
378 "\xB1\x04\x5A\xC4\x6D\x56\x1C\xD9\x64\xE7\x85\x7F\x88\x91\xC9\x60"
401 "\x5d\x59\xc3\x62\xd5\xa6\xda\x38\x26\x22\x5e\x34\x1c\x94\xaf\x98",
[all …]
/linux/lib/crypto/
H A Daesgcm.c43 * Returns: 0 on success, or -EINVAL if @keysize or @authsize contain values
60 return 0; in aesgcm_expandkey()
67 while (len > 0) { in aesgcm_ghash()
114 while (len > 0) { in aesgcm_crypt()
225 "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
235 "\x21\xd5\x14\xb2\x54\x66\x93\x1c"
247 "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
257 "\x21\xd5\x14\xb2\x54\x66\x93\x1c"
270 "\x1c\x26\x7e\x43\x84\xb0\xf6\x00"
279 "\x1c\x3c\x0c\x95\x95\x68\x09\x53"
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]

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