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/linux/drivers/mtd/spi-nor/
H A Deon.c13 .id = SNOR_ID(0x1c, 0x20, 0x16),
17 .id = SNOR_ID(0x1c, 0x20, 0x17),
21 .id = SNOR_ID(0x1c, 0x30, 0x14),
26 .id = SNOR_ID(0x1c, 0x30, 0x16),
30 .id = SNOR_ID(0x1c, 0x30, 0x17),
35 .id = SNOR_ID(0x1c, 0x31, 0x16),
41 .id = SNOR_ID(0x1c, 0x38, 0x17),
45 .id = SNOR_ID(0x1c, 0x70, 0x15),
50 .id = SNOR_ID(0x1c, 0x70, 0x16),
54 .id = SNOR_ID(0x1c, 0x70, 0x17),
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h27 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
28 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
29 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE__SHIFT 0x8
30 …A_PIXCLK_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
31 …_RESYNC_CNTL__PHYPLLA_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
32 …_RESYNC_CNTL__PHYPLLA_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
33 …_RESYNC_CNTL__PHYPLLA_PIXCLK_ENABLE_MASK 0x00000100L
34 …_RESYNC_CNTL__PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
36 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
37 …B_PIXCLK_RESYNC_CNTL__PHYPLLB_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
[all …]
H A Ddcn_2_0_0_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
37 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
38 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
H A Ddcn_3_0_1_sh_mask.h27 …_CAPABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED__SHIFT 0x0
28 …_CAPABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS__SHIFT 0x1
29 …_CAPABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED__SHIFT 0x3
30 …_CAPABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED__SHIFT 0x8
31 …_CAPABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED__SHIFT 0xc
32 …ABILITIES__SIXTY_FOUR_BIT_ADDRESS_SUPPORTED_MASK 0x0001L
33 …ABILITIES__NUMBER_OF_SERIAL_DATA_OUTPUT_SIGNALS_MASK 0x0006L
34 …ABILITIES__NUMBER_OF_BIDIRECTIONAL_STREAMS_SUPPORTED_MASK 0x00F8L
35 …ABILITIES__NUMBER_OF_INPUT_STREAMS_SUPPORTED_MASK 0x0F00L
36 …ABILITIES__NUMBER_OF_OUTPUT_STREAMS_SUPPORTED_MASK 0xF000L
[all …]
H A Ddcn_3_5_1_sh_mask.h6 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
7 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
8 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
9 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
10 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
11 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
12 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
13 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
14 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
15 …LLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
[all …]
H A Ddcn_3_5_0_sh_mask.h27 …ROLLER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER__SHIFT 0x0
28 …ER0_CORB_WRITE_POINTER__CORB_WRITE_POINTER_MASK 0x00FFL
29 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER__SHIFT 0x0
30 …ROLLER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET__SHIFT 0xf
31 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_MASK 0x00FFL
32 …ER0_CORB_READ_POINTER__CORB_READ_POINTER_RESET_MASK 0x8000L
33 …ROLLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE__SHIFT 0x0
34 …ROLLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE__SHIFT 0x1
35 …LLER0_CORB_CONTROL__CORB_MEMORY_ERROR_INTERRUPT_ENABLE_MASK 0x01L
36 …LLER0_CORB_CONTROL__ENABLE_CORB_DMA_ENGINE_MASK 0x02L
[all …]
H A Ddcn_2_1_0_sh_mask.h27 …M_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR__SHIFT 0x0
28 …_WRITE_PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR__SHIFT 0x10
29 …PAGE_ADDR__VGA_MEM_WRITE_PAGE0_ADDR_MASK 0x000003FFL
30 …PAGE_ADDR__VGA_MEM_WRITE_PAGE1_ADDR_MASK 0x03FF0000L
32 …M_READ_PAGE_ADDR__VGA_MEM_READ_PAGE0_ADDR__SHIFT 0x0
33 …_READ_PAGE_ADDR__VGA_MEM_READ_PAGE1_ADDR__SHIFT 0x10
34 …AGE_ADDR__VGA_MEM_READ_PAGE0_ADDR_MASK 0x000003FFL
35 …AGE_ADDR__VGA_MEM_READ_PAGE1_ADDR_MASK 0x03FF0000L
38 …NDER_CONTROL__VGA_BLINK_RATE__SHIFT 0x0
39 …NDER_CONTROL__VGA_BLINK_MODE__SHIFT 0x5
[all …]
/linux/drivers/video/fbdev/via/
H A Dhw.c13 {19, 19, 4, 0},
14 {26, 102, 5, 0},
15 {53, 112, 6, 0},
16 {41, 100, 7, 0},
17 {83, 108, 8, 0},
18 {87, 118, 9, 0},
19 {95, 115, 12, 0},
20 {108, 108, 13, 0},
21 {83, 83, 17, 0},
22 {67, 98, 20, 0},
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vpe/
H A Dvpe_6_1_0_sh_mask.h29 …EC_START__START__SHIFT 0x0
30 …__START_MASK 0xFFFFFFFFL
32 …CODE_ADDR__VALUE__SHIFT 0x0
33 …CODE_ADDR__THID__SHIFT 0xf
34 …R__VALUE_MASK 0x00001FFFL
35 …R__THID_MASK 0x00008000L
37 …CODE_DATA__VALUE__SHIFT 0x0
38 …A__VALUE_MASK 0xFFFFFFFFL
40 …32_CNTL__HALT__SHIFT 0x0
41 …32_CNTL__TH0_CHECKSUM_CLR__SHIFT 0x8
[all …]
/linux/arch/mips/include/asm/
H A Dcacheops.h18 #define CacheOp_Cache 0x03
19 #define CacheOp_Op 0x1c
21 #define Cache_I 0x00
22 #define Cache_D 0x01
23 #define Cache_T 0x02
24 #define Cache_V 0x02 /* Loongson-3 */
25 #define Cache_S 0x03
27 #define Index_Writeback_Inv 0x00
28 #define Index_Load_Tag 0x04
29 #define Index_Store_Tag 0x08
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_7_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_0_0_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_2_0_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_3_0_3_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_2_0_3_sh_mask.h26 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
30 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
35 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_sh_mask.h29 …DEC_START__START__SHIFT 0x0
30 …T__START_MASK 0xFFFFFFFFL
32 …F32_MISC_CNTL__F32_WAKEUP__SHIFT 0x0
33 …_CNTL__F32_WAKEUP_MASK 0x00000001L
35 …UCODE_VERSION__T0_UCODE_VERSION__SHIFT 0x0
36 …CODE_VERSION__T1_UCODE_VERSION__SHIFT 0x10
37 …RSION__T0_UCODE_VERSION_MASK 0x0000FFFFL
38 …RSION__T1_UCODE_VERSION_MASK 0xFFFF0000L
40 …GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0
41 …IMESTAMP_LO__DATA_MASK 0xFFFFFFFFL
[all …]
H A Dgc_12_0_0_sh_mask.h29 …DEC_START__START__SHIFT 0x0
30 …T__START_MASK 0xFFFFFFFFL
32 …MCU_MISC_CNTL__MCU_WAKEUP__SHIFT 0x0
33 …_CNTL__MCU_WAKEUP_MASK 0x00000001L
35 …UCODE_REV__CL__SHIFT 0x0
36 …CODE_REV__VARIANT_ID__SHIFT 0x1c
37 …V__CL_MASK 0x0FFFFFFFL
38 …V__VARIANT_ID_MASK 0xF0000000L
40 …GLOBAL_TIMESTAMP_LO__DATA__SHIFT 0x0
41 …IMESTAMP_LO__DATA_MASK 0xFFFFFFFFL
[all …]
/linux/lib/crypto/tests/
H A Dsha256-testvecs.h9 .data_len = 0,
11 0xe3, 0xb0, 0xc4, 0x42, 0x98, 0xfc, 0x1c, 0x14,
12 0x9a, 0xfb, 0xf4, 0xc8, 0x99, 0x6f, 0xb9, 0x24,
13 0x27, 0xae, 0x41, 0xe4, 0x64, 0x9b, 0x93, 0x4c,
14 0xa4, 0x95, 0x99, 0x1b, 0x78, 0x52, 0xb8, 0x55,
20 0x45, 0xf8, 0x3d, 0x17, 0xe1, 0x0b, 0x34, 0xfc,
21 0xa0, 0x1e, 0xb8, 0xf4, 0x45, 0x4d, 0xac, 0x34,
22 0xa7, 0x77, 0xd9, 0x40, 0x4a, 0x46, 0x4e, 0x73,
23 0x2c, 0xf4, 0xab, 0xf2, 0xc0, 0xda, 0x94, 0xc4,
29 0xf9, 0xd3, 0x52, 0x2f, 0xd5, 0xe0, 0x99, 0x15,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]

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