Lines Matching +full:0 +full:x1c
18 #define CacheOp_Cache 0x03
19 #define CacheOp_Op 0x1c
21 #define Cache_I 0x00
22 #define Cache_D 0x01
23 #define Cache_T 0x02
24 #define Cache_V 0x02 /* Loongson-3 */
25 #define Cache_S 0x03
27 #define Index_Writeback_Inv 0x00
28 #define Index_Load_Tag 0x04
29 #define Index_Store_Tag 0x08
30 #define Hit_Invalidate 0x10
31 #define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
32 #define Hit_Writeback 0x18
50 #define Create_Dirty_Excl_D (Cache_D | 0x0c)
51 #define Fill_I (Cache_I | 0x14)
58 #define Cache_SI 0x02
59 #define Cache_SD 0x03
67 #define Create_Dirty_Excl_SD (Cache_SD | 0x0c)
72 #define Hit_Set_Virtual_SI (Cache_SI | 0x1c)
73 #define Hit_Set_Virtual_SD (Cache_SD | 0x1c)
78 #define R5K_Page_Invalidate_S (Cache_S | 0x14)
83 #define Page_Invalidate_T (Cache_T | 0x14)
90 * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
97 #define Cache_Barrier 0x14
99 #define Index_Load_Data_I (Cache_I | 0x18)
100 #define Index_Load_Data_D (Cache_D | 0x18)
101 #define Index_Load_Data_S (Cache_S | 0x18)
102 #define Index_Store_Data_I (Cache_I | 0x1c)
103 #define Index_Store_Data_D (Cache_D | 0x1c)
104 #define Index_Store_Data_S (Cache_S | 0x1c)
109 #define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)