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/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,ethsys.yaml52 reg = <0x1b000000 0x1000>;
H A Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/linux/Documentation/devicetree/bindings/dma/
H A Dapm-xgene-dma.txt27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
78 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/linux/arch/powerpc/crypto/
H A Daesp10-ppc.pl103 $LITTLE_ENDIAN = ($flavour=~/le$/) ? $SIZE_T : 0;
105 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
121 my ($zero,$in0,$in1,$key,$rcon,$mask,$tmp)=map("v$_",(0..6));
131 .long 0x01000000, 0x01000000, 0x01000000, 0x01000000 ?rev
132 .long 0x1b000000, 0x1b000000, 0x1b000000, 0x1b000000 ?rev
133 .long 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c ?rev
134 .long 0,0,0,0 ?asis
139 addi $ptr,$ptr,-0x48
142 .long 0
143 .byte 0,12,0x14,0,0,0,0,0
[all …]
H A Daesp8-ppc.pl103 $LITTLE_ENDIAN = ($flavour=~/le$/) ? $SIZE_T : 0;
105 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1;
121 my ($zero,$in0,$in1,$key,$rcon,$mask,$tmp)=map("v$_",(0..6));
131 .long 0x01000000, 0x01000000, 0x01000000, 0x01000000 ?rev
132 .long 0x1b000000, 0x1b000000, 0x1b000000, 0x1b000000 ?rev
133 .long 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c, 0x0d0e0f0c ?rev
134 .long 0,0,0,0 ?asis
135 .long 0x0f102132, 0x43546576, 0x8798a9ba, 0xcbdcedfe
140 addi $ptr,$ptr,-0x58
143 .long 0
[all …]
/linux/arch/arm/configs/
H A Dlpc18xx_defconfig21 CONFIG_DRAM_BASE=0x28000000
22 CONFIG_DRAM_SIZE=0x02000000
23 CONFIG_FLASH_MEM_BASE=0x1b000000
24 CONFIG_FLASH_SIZE=0x00080000
/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/linux/arch/arc/boot/dts/
H A Daxc001.dtsi23 ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
26 #clock-cells = <0>;
32 #clock-cells = <0>;
49 reg = < 0x2000 0x80 >;
51 #size-cells = <0>;
53 ictl_intc: gpio-controller@0 {
58 reg = <0>;
68 reg = <0x5000 0x100>;
97 reg = < 0x0 0xe0012000 0x0 0x200 >;
106 reg = <0x0 0x80000000 0x0 0x1b000000>; /* (512 - 32) MiB */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl9301-switch.yaml51 'reboot@[0-9a-f]+$':
54 'i2c@[0-9a-f]+$':
57 'mdio-controller@[0-9a-f]+$':
72 reg = <0x1b000000 0x10000>;
81 reg = <0x0c 0x4>;
82 value = <0x01>;
87 reg = <0x36c 0x14>;
89 #size-cells = <0>;
91 i2c@0 {
92 reg = <0>;
[all …]
/linux/arch/mips/alchemy/devboards/
H A Ddb1000.c50 return 0; in db1000_board_setup()
57 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
60 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
75 [0] = {
77 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
89 .id = 0,
100 [0] = {
102 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
114 .id = 0,
124 [0] = {
[all …]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi16 #address-cells = <0>;
23 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 reg = <0x1b000000 0x10000>;
57 reg = <0x0c 0x4>;
58 value = <0x01>;
63 reg = <0x36c 0x14>;
[all …]
/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux/arch/mips/sni/
H A Drm200.c37 MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
38 MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
52 .start = 0x1cd41ffc,
53 .end = 0x1cd41fff,
66 .start = 0x18000000,
67 .end = 0x180fffff,
71 .start = 0x1b000000,
72 .end = 0x1b000004,
76 .start = 0x1ff00000,
77 .end = 0x1ff00020,
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
H A Dmt2701.dtsi25 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
36 reg = <0x1>;
41 reg = <0x2>;
46 reg = <0x3>;
57 reg = <0 0x80002000 0 0x1000>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
73 clk26m: oscillator@0 {
[all …]
/linux/arch/arm64/include/asm/
H A Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
/linux/arch/mips/boot/dts/img/
H A Dpistachio.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0>;
46 reg = <0x18100000 0x200>;
56 pinctrl-0 = <&i2c0_pins>;
59 #size-cells = <0>;
64 reg = <0x18100200 0x200>;
74 pinctrl-0 = <&i2c1_pins>;
77 #size-cells = <0>;
82 reg = <0x18100400 0x200>;
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
140 reg = <0 0x43000000 0 0x30000>;
150 thermal-sensors = <&thermal 0>;
216 reg = <0 0x10000000 0 0x1000>;
223 reg = <0 0x10001000 0 0x250>;
[all …]
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]