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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
61 reg = <0x13410000 0x10000>;
64 ranges = <1 0 0x1b000000 0x1000000>,
65 <2 0 0x1a000000 0x1000000>,
66 <3 0 0x19000000 0x1000000>,
67 <4 0 0x18000000 0x1000000>,
68 <5 0 0x17000000 0x1000000>,
69 <6 0 0x16000000 0x1000000>;
78 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus-clock.dtsi39 #clock-cells = <0>;
46 #clock-cells = <0>;
49 reg = <0x19000000 0x1000>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
73 reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
81 #clock-cells = <0>;
90 #clock-cells = <0>;
100 reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
109 reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
[all …]
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
H A Dbcm-ns.dtsi26 ranges = <0x00000000 0x18000000 0x00001000>;
32 reg = <0x0300 0x100>;
40 reg = <0x0400 0x100>;
44 pinctrl-0 = <&pinmux_uart1>;
51 ranges = <0x00000000 0x19000000 0x00023000>;
57 reg = <0x20000 0x100>;
62 reg = <0x20200 0x100>;
69 reg = <0x20600 0x20>;
78 #address-cells = <0>;
80 reg = <0x21000 0x1000>,
[all …]
H A Dbcm-cygnus.dtsi48 memory@0 {
50 reg = <0 0>;
55 #size-cells = <0>;
57 cpu@0 {
61 reg = <0x0>;
74 ranges = <0x00000000 0x19000000 0x1000000>;
80 reg = <0x20200 0x100>;
88 #address-cells = <0>;
90 reg = <0x21000 0x1000>,
91 <0x20100 0x100>;
[all …]
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar71xx.yaml78 reg = <0x19000000 0x200>;
90 reg = <0x1a000000 0x200>;
106 #size-cells = <0>;
110 reg = <0x10>;
122 #size-cells = <0>;
124 switch_port0: port@0 {
125 reg = <0x0>;
137 reg = <0x1>;
143 reg = <0x2>;
149 reg = <0x3>;
[all …]
/linux/arch/mips/sni/
H A Da20r.c30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
45 .start = 0x1c081ffc,
46 .end = 0x1c081fff,
59 .start = 0x18000000,
60 .end = 0x18000004,
64 .start = 0x18010000,
65 .end = 0x18010004,
69 .start = 0x1ff00000,
70 .end = 0x1ff00020,
[all …]
H A Drm200.c37 MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
38 MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
52 .start = 0x1cd41ffc,
53 .end = 0x1cd41fff,
66 .start = 0x18000000,
67 .end = 0x180fffff,
71 .start = 0x1b000000,
72 .end = 0x1b000004,
76 .start = 0x1ff00000,
77 .end = 0x1ff00020,
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp1022ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
51 reg = <0x03000000 0x00e00000>;
57 reg = <0x03e00000 0x00200000>;
63 reg = <0x04000000 0x00400000>;
69 reg = <0x04400000 0x03b00000>;
74 reg = <0x07f00000 0x00080000>;
80 reg = <0x07f80000 0x00080000>;
[all …]
/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux/arch/mips/boot/dts/ingenic/
H A Djz4780.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
18 reg = <0>;
26 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
35 #address-cells = <0>;
43 reg = <0x10001000 0x50>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10000000 0x100>;
[all …]
/linux/drivers/net/usb/
H A Dlan78xx.h9 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
10 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
11 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
32 #define TX_CMD_A_IGE_ (0x20000000)
33 #define TX_CMD_A_ICE_ (0x10000000)
34 #define TX_CMD_A_LSO_ (0x08000000)
35 #define TX_CMD_A_IPE_ (0x04000000)
36 #define TX_CMD_A_TPE_ (0x02000000)
37 #define TX_CMD_A_IVTG_ (0x01000000)
38 #define TX_CMD_A_RVTG_ (0x00800000)
[all …]
/linux/arch/mips/alchemy/devboards/
H A Ddb1300.c39 #define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
57 #define DB1300_ETH_PHYS_ADDR 0x19000000
58 #define DB1300_ETH_PHYS_END 0x197fffff
61 #define DB1300_IDE_PHYS_ADDR 0x18800000
66 #define DB1300_NAND_PHYS_ADDR 0x20000000
67 #define DB1300_NAND_PHYS_END 0x20000fff
71 { I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
72 { I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
85 /* wake-from-str pins 0-3 */
137 i = &db1300_dev_pins[0]; in db1300_gpio_config()
[all …]
/linux/arch/hexagon/kernel/
H A Dvm_init_segtable.S16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
/linux/drivers/net/ethernet/atheros/
H A Dag71xx.c70 #define AG71XX_REG_MAC_CFG1 0x0000
71 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
81 #define AG71XX_REG_MAC_CFG2 0x0004
82 #define MAC_CFG2_FDX BIT(0)
88 #define AG71XX_REG_MAC_MFL 0x0010
90 #define AG71XX_REG_MII_CFG 0x0020
91 #define MII_CFG_CLK_DIV_4 0
108 #define AG71XX_REG_MII_CMD 0x0024
109 #define MII_CMD_READ BIT(0)
111 #define AG71XX_REG_MII_ADDR 0x0028
[all …]
/linux/drivers/bluetooth/
H A Dhci_bcm4377.c26 BCM4377 = 0,
32 #define BCM4377_DEVICE_ID 0x5fa0
33 #define BCM4378_DEVICE_ID 0x5f69
34 #define BCM4387_DEVICE_ID 0x5f71
35 #define BCM4388_DEVICE_ID 0x5f72
43 * 0xffffffff but is always aligned down to the previous 0x200 byte boundary
44 * which effectively limits the window to [start, start+0xfffffe00].
45 * We just limit the DMA window to [0, 0xfffffe00] to make sure we don't
48 #define BCM4377_DMA_MASK 0xfffffe00
50 #define BCM4377_PCIECFG_BAR0_WINDOW1 0x80
[all …]