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/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dqcom,ath10k.txt95 - qcom,coexist-support : should contain eithr "0" or "1" to indicate coex
116 pcie@0 {
117 reg = <0 0 0 0 0>;
123 wifi@0,0 {
124 reg = <0 0 0 0 0>;
135 reg = <0xa000000 0x200000>;
154 interrupts = <0 0x20 0x1>,
155 <0 0x21 0x1>,
156 <0 0x22 0x1>,
157 <0 0x23 0x1>,
[all …]
H A Dqcom,ath10k.yaml136 enum: [0, 1]
303 reg = <0x18800000 0x800000>;
320 iommus = <&anoc2_smmu 0x1900>,
321 <&anoc2_smmu 0x1901>;
330 iommus = <&apps_smmu 0x1c02 0x1>;
340 reg = <0xa000000 0x200000>;
/freebsd/sys/contrib/dev/rtw89/
H A Dmac.h12 #define MAC_MEM_DUMP_PAGE_SIZE_AX 0x40000
13 #define MAC_MEM_DUMP_PAGE_SIZE_BE 0x80000
15 #define ADDR_CAM_ENT_SIZE 0x40
16 #define ADDR_CAM_ENT_SHORT_SIZE 0x20
17 #define BSSID_CAM_ENT_SIZE 0x08
22 RTW89_DMAC_SEL = 0,
29 RTW89_FWD_DONT_CARE = 0,
45 RTW89_MAC_WD_DMA_INTVL_DEF = 0xFE
57 RTW89_MAC_TAG_NUM_DEF = 0xFE
61 RTW89_MAC_LBC_TMR_8US = 0,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7996/
H A Dregs.h84 #define MT_RRO_TOP_BASE 0xA000
87 #define MT_RRO_BA_BITMAP_BASE0 MT_RRO_TOP(0x8)
88 #define MT_RRO_BA_BITMAP_BASE1 MT_RRO_TOP(0xC)
89 #define WF_RRO_AXI_MST_CFG MT_RRO_TOP(0xB8)
91 #define MT_RRO_ADDR_ARRAY_BASE1 MT_RRO_TOP(0x34)
94 #define MT_RRO_IND_CMD_SIGNATURE_BASE0 MT_RRO_TOP(0x38)
95 #define MT_RRO_IND_CMD_SIGNATURE_BASE1 MT_RRO_TOP(0x3C)
96 #define MT_RRO_IND_CMD_0_CTRL0 MT_RRO_TOP(0x40)
99 #define MT_RRO_PARTICULAR_CFG0 MT_RRO_TOP(0x5C)
100 #define MT_RRO_PARTICULAR_CFG1 MT_RRO_TOP(0x60)
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h130 #define MT_MCU_WFDMA0_BASE 0x2000
133 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
136 #define MT_MCU_WFDMA1_BASE 0x3000
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
146 #define MT_PLE_BASE 0x820c0000
149 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
154 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
155 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
165 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
167 #define MT_PSE_BASE 0x820c8000
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm630.dtsi36 #clock-cells = <0>;
43 #clock-cells = <0>;
51 #size-cells = <0>;
56 reg = <0x0 0x100>;
76 reg = <0x0 0x101>;
91 reg = <0x0 0x102>;
106 reg = <0x0 0x103>;
118 cpu4: cpu@0 {
121 reg = <0x0 0x0>;
141 reg = <0x0 0x1>;
[all …]
H A Dmsm8998.dtsi17 qcom,msm-id = <292 0x0>;
27 reg = <0x0 0x80000000 0x0 0x0>;
36 reg = <0x0 0x85800000 0x0 0x600000>;
41 reg = <0x0 0x85e00000 0x0 0x100000>;
46 reg = <0x0 0x86000000 0x0 0x200000>;
51 reg = <0x0 0x86200000 0x0 0x2d00000>;
57 reg = <0x0 0x88f00000 0x0 0x200000>;
65 reg = <0x0 0x8ab00000 0x0 0x700000>;
70 reg = <0x0 0x8b200000 0x0 0x1a00000>;
75 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
H A Dsm6350.dtsi35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi31 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
90 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi35 #clock-cells = <0>;
42 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
61 qcom,freq-domain = <&cpufreq_hw 0>;
63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
84 reg = <0x0 0x100>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]