Searched +full:0 +full:x18220000 (Results 1 – 13 of 13) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/soc/qcom/ |
| H A D | qcom,rpmh-rsc.yaml | 84 enum: [ 0, 1, 2, 3 ] 103 - const: drv-0 121 '^regulators(-[0-9])?$': 153 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of 154 // 2, the register offsets for DRV2 start at 0D00, the register 156 // DRV0: 0x179C0000 157 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000 158 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000 159 // TCS-OFFSET: 0xD00 165 reg = <0x179c0000 0x10000>, [all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | qcs615.dtsi | 23 #size-cells = <0>; 25 cpu0: cpu@0 { 28 reg = <0x0 0x0>; 48 reg = <0x0 0x100>; 67 reg = <0x0 0x200>; 86 reg = <0x0 0x300>; 105 reg = <0x0 0x400>; 124 reg = <0x0 0x500>; 143 reg = <0x0 0x600>; 163 reg = <0x0 0x700>; [all …]
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| H A D | sm6350.dtsi | 35 #clock-cells = <0>; 43 #clock-cells = <0>; 49 #size-cells = <0>; 51 cpu0: cpu@0 { 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 90 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sc8180x.dtsi | 31 #clock-cells = <0>; 37 #clock-cells = <0>; 45 #size-cells = <0>; 47 cpu0: cpu@0 { 50 reg = <0x0 0x0>; 54 qcom,freq-domain = <&cpufreq_hw 0>; 61 clocks = <&cpufreq_hw 0>; 79 reg = <0x0 0x100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 90 clocks = <&cpufreq_hw 0>; [all …]
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| H A D | sm8350.dtsi | 40 #clock-cells = <0>; 48 #clock-cells = <0>; 54 #size-cells = <0>; 56 cpu0: cpu@0 { 59 reg = <0x0 0x0>; 60 clocks = <&cpufreq_hw 0>; 63 qcom,freq-domain = <&cpufreq_hw 0>; 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; 87 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sc7180.dtsi | 67 #clock-cells = <0>; 73 #clock-cells = <0>; 79 #size-cells = <0>; 81 cpu0: cpu@0 { 84 reg = <0x0 0x0>; 85 clocks = <&cpufreq_hw 0>; 96 qcom,freq-domain = <&cpufreq_hw 0>; 113 reg = <0x0 0x100>; 114 clocks = <&cpufreq_hw 0>; 125 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sm8150.dtsi | 35 #clock-cells = <0>; 42 #clock-cells = <0>; 50 #size-cells = <0>; 52 cpu0: cpu@0 { 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; [all …]
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| H A D | qcs8300.dtsi | 30 #clock-cells = <0>; 36 #clock-cells = <0>; 43 #size-cells = <0>; 45 cpu0: cpu@0 { 48 reg = <0x0 0x0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 68 reg = <0x0 0x100>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 88 reg = <0x0 0x200>; 108 reg = <0x0 0x300>; [all …]
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| H A D | sc8280xp.dtsi | 33 #clock-cells = <0>; 38 #clock-cells = <0>; 45 #size-cells = <0>; 47 cpu0: cpu@0 { 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| H A D | sm8250.dtsi | 81 #clock-cells = <0>; 89 #clock-cells = <0>; 95 #size-cells = <0>; 97 cpu0: cpu@0 { 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 116 cache-size = <0x20000>; 122 cache-size = <0x400000>; [all …]
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| H A D | sc7280.dtsi | 83 #clock-cells = <0>; 89 #clock-cells = <0>; 100 reg = <0x0 0x004cd000 0x0 0x1000>; 104 reg = <0x0 0x80000000 0x0 0x600000>; 109 reg = <0x0 0x80600000 0x0 0x200000>; 114 reg = <0x0 0x80800000 0x0 0x60000>; 119 reg = <0x0 0x80860000 0x0 0x20000>; 125 reg = <0x0 0x80884000 0x0 0x10000>; 130 reg = <0x0 0x808ff000 0x0 0x1000>; 135 reg = <0x0 0x80900000 0x0 0x200000>; [all …]
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| H A D | sa8775p.dtsi | 33 #clock-cells = <0>; 38 #clock-cells = <0>; 44 #size-cells = <0>; 46 cpu0: cpu@0 { 49 reg = <0x0 0x0>; 53 qcom,freq-domain = <&cpufreq_hw 0>; 78 reg = <0x0 0x100>; 82 qcom,freq-domain = <&cpufreq_hw 0>; 102 reg = <0x0 0x200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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| /freebsd/tools/test/iconv/ref/ |
| H A D | UTF-32BE-rev | 1 0x00 = 0x00000000 2 0x01 = 0x01000000 3 0x02 = 0x02000000 4 0x03 = 0x03000000 5 0x04 = 0x04000000 6 0x05 = 0x05000000 7 0x06 = 0x06000000 8 0x07 = 0x07000000 9 0x08 = 0x08000000 10 0x09 = 0x09000000 [all …]
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