Searched +full:0 +full:x18050000 (Results 1 – 6 of 6) sorted by relevance
26 reg = <0x18050000 0x20>;
65 reg = <0x18050000 0x20>;
12 #size-cells = <0>;14 cpu@0 {18 reg = <0>;30 <&ddr_ctrl 0>, <&ddr_ctrl 1>;54 reg = <0x18000000 0x100>;61 reg = <0x18020000 0x20>;77 reg = <0x18040000 0x30>;92 reg = <0x18050000 0x20>;103 reg = <0x18060008 0x8>;114 reg = <0x18060010 0x8>;[all …]
12 #size-cells = <0>;14 cpu@0 {18 reg = <0>;34 #clock-cells = <0>;57 reg = <0x18000000 0x100>;64 reg = <0x18020000 0x14>;76 reg = <0x18040000 0x34>;92 reg = <0x18050000 0x100>;102 reg = <0x18060010 0x8>;113 reg = <0x1806001c 0x4>;[all …]
130 #define MT_MCU_WFDMA0_BASE 0x2000133 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)136 #define MT_MCU_WFDMA1_BASE 0x3000140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)146 #define MT_PLE_BASE 0x820c0000149 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)154 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)155 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)165 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))167 #define MT_PSE_BASE 0x820c8000[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]