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12

/linux/sound/pci/echoaudio/
H A Dmona.c21 #define PX_ANALOG_OUT 0 /* 6 */
28 #define BX_ANALOG_OUT 0 /* 6 */
63 #define FW_361_LOADER 0
73 {0, "loader_dsp.fw"},
74 {0, "mona_301_dsp.fw"},
75 {0, "mona_361_dsp.fw"},
76 {0, "mona_301_1_asic_48.fw"},
77 {0, "mona_301_1_asic_96.fw"},
78 {0, "mona_361_1_asic_48.fw"},
79 {0, "mona_361_1_asic_96.fw"},
[all …]
H A Ddarla24.c17 #define PX_ANALOG_OUT 0 /* 8 */
18 #define PX_DIGITAL_OUT 8 /* 0 */
20 #define PX_DIGITAL_IN 10 /* 0 */
24 #define BX_ANALOG_OUT 0 /* 8 */
25 #define BX_DIGITAL_OUT 8 /* 0 */
27 #define BX_DIGITAL_IN 10 /* 0 */
52 #define FW_DARLA24_DSP 0
55 {0, "darla24_dsp.fw"}
59 {0x1057, 0x1801, 0xECC0, 0x0040, 0, 0, 0}, /* DSP 56301 Darla24 rev.0 */
60 {0x1057, 0x1801, 0xECC0, 0x0041, 0, 0, 0}, /* DSP 56301 Darla24 rev.1 */
[all …]
H A Dlayla20.c22 #define PX_ANALOG_OUT 0 /* 10 */
29 #define BX_ANALOG_OUT 0 /* 10 */
59 #define FW_LAYLA20_DSP 0
63 {0, "layla20_dsp.fw"},
64 {0, "layla20_asic.fw"}
68 {0x1057, 0x1801, 0xECC0, 0x0030, 0, 0, 0}, /* DSP 56301 Layla20 rev.0 */
69 {0x1057, 0x1801, 0xECC0, 0x0031, 0, 0, 0}, /* DSP 56301 Layla20 rev.1 */
70 {0,}
H A Dgina24.c23 #define PX_ANALOG_OUT 0 /* 8 */
30 #define BX_ANALOG_OUT 0 /* 8 */
62 #define FW_361_LOADER 0
69 {0, "loader_dsp.fw"},
70 {0, "gina24_301_dsp.fw"},
71 {0, "gina24_361_dsp.fw"},
72 {0, "gina24_301_asic.fw"},
73 {0, "gina24_361_asic.fw"}
77 {0x1057, 0x1801, 0xECC0, 0x0050, 0, 0, 0}, /* DSP 56301 Gina24 rev.0 */
78 {0x1057, 0x1801, 0xECC0, 0x0051, 0, 0, 0}, /* DSP 56301 Gina24 rev.1 */
[all …]
H A Ddarla20.c13 #define PX_ANALOG_OUT 0 /* 8 */
14 #define PX_DIGITAL_OUT 8 /* 0 */
16 #define PX_DIGITAL_IN 10 /* 0 */
20 #define BX_ANALOG_OUT 0 /* 8 */
21 #define BX_DIGITAL_OUT 8 /* 0 */
23 #define BX_DIGITAL_IN 10 /* 0 */
48 #define FW_DARLA20_DSP 0
51 {0, "darla20_dsp.fw"}
55 {0x1057, 0x1801, 0xECC0, 0x0010, 0, 0, 0}, /* DSP 56301 Darla20 rev.0 */
56 {0,}
H A Dgina20.c17 #define PX_ANALOG_OUT 0 /* 8 */
24 #define BX_ANALOG_OUT 0 /* 8 */
52 #define FW_GINA20_DSP 0
55 {0, "gina20_dsp.fw"}
59 {0x1057, 0x1801, 0xECC0, 0x0020, 0, 0, 0}, /* DSP 56301 Gina20 rev.0 */
60 {0,}
H A Dechoaudio.h99 0-7 Analog outputs (0 .. FirstDigitalBusOut-1)
169 #define VENDOR_ID 0x1057
170 #define DEVICE_ID_56301 0x1801
171 #define DEVICE_ID_56361 0x3410
172 #define SUBVENDOR_ID 0xECC0
178 #define DARLA20 0x0010
179 #define GINA20 0x0020
180 #define LAYLA20 0x0030
181 #define DARLA24 0x0040
182 #define GINA24 0x0050
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6apm-dai.yaml33 iommus = <&apps_smmu 0x1801 0x0>;
H A Dqcom,q6apm.yaml35 const: 0
50 #size-cells = <0>;
55 #sound-dai-cells = <0>;
60 iommus = <&apps_smmu 0x1801 0x0>;
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,apr.yaml89 const: 0
156 #size-cells = <0>;
177 #size-cells = <0>;
193 #size-cells = <0>;
198 #sound-dai-cells = <0>;
203 iommus = <&apps_smmu 0x1801 0x0>;
/linux/Documentation/devicetree/bindings/perf/
H A Driscv,pmu.yaml78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
/linux/arch/powerpc/boot/
H A Dcuboot-pq2.c73 if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr, in update_cs_ranges()
79 for (i = 0; i < len / sizeof(struct cs_range); i++) { in update_cs_ranges()
85 if (cs_ranges_buf[i].base != 0) in update_cs_ranges()
94 base &= 0x7fff; in update_cs_ranges()
95 option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff; in update_cs_ranges()
97 base = 0x1801; in update_cs_ranges()
98 option = 0x10; in update_cs_ranges()
101 out_be32(&ctrl_addr[cs * 2], 0); in update_cs_ranges()
134 for (i = 0; i < 3; i++) in fixup_pci()
158 for (i = 0; i < len / sizeof(struct pci_range); i++) { in fixup_pci()
[all …]
/linux/sound/soc/codecs/
H A Dwm8961.c30 #define WM8961_MAX_REGISTER 0xFC
33 { 0, 0x009F }, /* R0 - Left Input volume */
34 { 1, 0x009F }, /* R1 - Right Input volume */
35 { 2, 0x0000 }, /* R2 - LOUT1 volume */
36 { 3, 0x0000 }, /* R3 - ROUT1 volume */
37 { 4, 0x0020 }, /* R4 - Clocking1 */
38 { 5, 0x0008 }, /* R5 - ADC & DAC Control 1 */
39 { 6, 0x0000 }, /* R6 - ADC & DAC Control 2 */
40 { 7, 0x000A }, /* R7 - Audio Interface 0 */
41 { 8, 0x01F4 }, /* R8 - Clocking2 */
[all …]
H A Drt5682s.h21 #define RT5682S_RESET 0x0000
22 #define RT5682S_VERSION_ID 0x00fd
23 #define RT5682S_VENDOR_ID 0x00fe
24 #define RT5682S_DEVICE_ID 0x00ff
26 #define RT5682S_HP_CTRL_1 0x0002
27 #define RT5682S_HP_CTRL_2 0x0003
28 #define RT5682S_HPL_GAIN 0x0005
29 #define RT5682S_HPR_GAIN 0x0006
31 #define RT5682S_I2C_CTRL 0x0008
34 #define RT5682S_CBJ_BST_CTRL 0x000b
[all …]
H A Drt1011.c37 { RT1011_POWER_9, 0xa840 },
39 { RT1011_ADC_SET_5, 0x0a20 },
40 { RT1011_DAC_SET_2, 0xa032 },
42 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
43 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
45 { RT1011_A_TIMING_1, 0x6054 },
47 { RT1011_POWER_7, 0x3e55 },
48 { RT1011_POWER_8, 0x0520 },
49 { RT1011_BOOST_CON_1, 0xe188 },
50 { RT1011_POWER_4, 0x16f2 },
[all …]
/linux/drivers/media/usb/siano/
H A Dsmsusb.c24 #define USB1_BUFFER_SIZE 0x1000
25 #define USB2_BUFFER_SIZE 0x2000
97 if ((urb->actual_length > 0) && (urb->status == 0)) { in smsusb_onresponse()
126 surb->cb->offset = 0; in smsusb_onresponse()
180 for (i = 0; i < MAX_URBS; i++) { in smsusb_stop_streaming()
196 for (i = 0; i < MAX_URBS; i++) { in smsusb_start_streaming()
198 if (rc < 0) { in smsusb_start_streaming()
257 if (id < 0) in smsusb1_load_firmware()
268 if (rc < 0) { in smsusb1_load_firmware()
274 if (rc < 0) { in smsusb1_load_firmware()
[all …]
/linux/drivers/rtc/
H A Drtc-abx80x.c22 #define ABX8XX_REG_HTH 0x00
23 #define ABX8XX_REG_SC 0x01
24 #define ABX8XX_REG_MN 0x02
25 #define ABX8XX_REG_HR 0x03
26 #define ABX8XX_REG_DA 0x04
27 #define ABX8XX_REG_MO 0x05
28 #define ABX8XX_REG_YR 0x06
29 #define ABX8XX_REG_WD 0x07
31 #define ABX8XX_REG_AHTH 0x08
32 #define ABX8XX_REG_ASC 0x09
[all …]
/linux/drivers/pcmcia/
H A Dti113x.h37 #define TI113X_SYSTEM_CONTROL 0x0080 /* 32 bit */
38 #define TI113X_SCR_SMIROUTE 0x04000000
39 #define TI113X_SCR_SMISTATUS 0x02000000
40 #define TI113X_SCR_SMIENB 0x01000000
41 #define TI113X_SCR_VCCPROT 0x00200000
42 #define TI113X_SCR_REDUCEZV 0x00100000
43 #define TI113X_SCR_CDREQEN 0x00080000
44 #define TI113X_SCR_CDMACHAN 0x00070000
45 #define TI113X_SCR_SOCACTIVE 0x00002000
46 #define TI113X_SCR_PWRSTREAM 0x00000800
[all …]
/linux/drivers/hid/
H A Dhid-ids.h17 #define USB_VENDOR_ID_258A 0x258a
18 #define USB_DEVICE_ID_258A_6A88 0x6a88
20 #define USB_VENDOR_ID_3M 0x0596
21 #define USB_DEVICE_ID_3M1968 0x0500
22 #define USB_DEVICE_ID_3M2256 0x0502
23 #define USB_DEVICE_ID_3M3266 0x0506
25 #define USB_VENDOR_ID_A4TECH 0x09da
26 #define USB_DEVICE_ID_A4TECH_WCP32PU 0x0006
27 #define USB_DEVICE_ID_A4TECH_X5_005D 0x000a
28 #define USB_DEVICE_ID_A4TECH_RP_649 0x001a
[all …]
/linux/include/linux/mfd/madera/
H A Dregisters.h14 #define MADERA_SOFTWARE_RESET 0x00
15 #define MADERA_HARDWARE_REVISION 0x01
16 #define MADERA_CTRL_IF_CFG_1 0x08
17 #define MADERA_CTRL_IF_CFG_2 0x09
18 #define MADERA_CTRL_IF_CFG_3 0x0A
19 #define MADERA_WRITE_SEQUENCER_CTRL_0 0x16
20 #define MADERA_WRITE_SEQUENCER_CTRL_1 0x17
21 #define MADERA_WRITE_SEQUENCER_CTRL_2 0x18
22 #define MADERA_TONE_GENERATOR_1 0x20
23 #define MADERA_TONE_GENERATOR_2 0x21
[all …]
/linux/drivers/media/i2c/
H A Dmt9p031.c37 #define MT9P031_CHIP_VERSION 0x00
38 #define MT9P031_CHIP_VERSION_VALUE 0x1801
39 #define MT9P031_ROW_START 0x01
40 #define MT9P031_ROW_START_MIN 0
43 #define MT9P031_COLUMN_START 0x02
44 #define MT9P031_COLUMN_START_MIN 0
47 #define MT9P031_WINDOW_HEIGHT 0x03
51 #define MT9P031_WINDOW_WIDTH 0x04
55 #define MT9P031_HORIZONTAL_BLANK 0x05
56 #define MT9P031_HORIZONTAL_BLANK_MIN 0
[all …]
/linux/sound/pci/
H A Dazt3328.c82 * some custom data starting at 0x80. What kind of config settings
90 * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
91 * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
92 * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
93 * - "timidity -iAv -B2,8 -Os -EFreverb=0"
94 * - "pmidi -p 128:0 jazz.mid"
105 * where a:b is the client number plus 0 usually, as given by aconnect above.
118 * - no DMA crackling on SiS735: 0x50DC/0x1801/16
119 * - unknown performance: 0x50DC/0x1801/10
217 "dump joy200 0x200 8", "dump mpu388 0x388 4", "dump joy 0xb400 8",
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800usb.c77 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800usb_stop_queue()
82 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800usb_stop_queue()
83 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800usb_stop_queue()
84 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800usb_stop_queue()
187 * magic value USB_MODE_AUTORUN (0x11) to the device, thus the in rt2800usb_autorun_detect()
191 USB_VENDOR_REQUEST_IN, 0, in rt2800usb_autorun_detect()
196 if (ret < 0) in rt2800usb_autorun_detect()
199 if ((fw_mode & 0x00000003) == 2) in rt2800usb_autorun_detect()
202 return 0; in rt2800usb_autorun_detect()
224 offset = 0; in rt2800usb_write_firmware()
[all …]
/linux/drivers/net/dsa/
H A Dlan9303-core.c20 /* For the LAN9303 and LAN9354, only port 0 is an XMII port. */
21 #define IS_PORT_XMII(port) ((port) == 0)
28 #define LAN9303_CHIP_REV 0x14
29 # define LAN9303_CHIP_ID 0x9303
30 # define LAN9352_CHIP_ID 0x9352
31 # define LAN9353_CHIP_ID 0x9353
32 # define LAN9354_CHIP_ID 0x9354
33 # define LAN9355_CHIP_ID 0x9355
34 #define LAN9303_IRQ_CFG 0x15
37 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
[all …]

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