20 /* For the LAN9303 and LAN9354, only port 0 is an XMII port. */
21 #define IS_PORT_XMII(port)	((port) == 0)
28 #define LAN9303_CHIP_REV 0x14
29 # define LAN9303_CHIP_ID 0x9303
30 # define LAN9352_CHIP_ID 0x9352
31 # define LAN9353_CHIP_ID 0x9353
32 # define LAN9354_CHIP_ID 0x9354
33 # define LAN9355_CHIP_ID 0x9355
34 #define LAN9303_IRQ_CFG 0x15
37 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
38 #define LAN9303_INT_STS 0x16
41 #define LAN9303_INT_EN 0x17
44 #define LAN9303_BYTE_ORDER 0x19
45 #define LAN9303_HW_CFG 0x1D
49 #define LAN9303_PMI_DATA 0x29
50 #define LAN9303_PMI_ACCESS 0x2A
51 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
52 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
53 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
55 #define LAN9303_MANUAL_FC_1 0x68
56 #define LAN9303_MANUAL_FC_2 0x69
57 #define LAN9303_MANUAL_FC_0 0x6a
61 #define LAN9303_SWITCH_CSR_DATA 0x6b
62 #define LAN9303_SWITCH_CSR_CMD 0x6c
66 #define LAN9303_VIRT_PHY_BASE 0x70
67 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
73 #define LAN9303_SW_DEV_ID 0x0000
74 #define LAN9303_SW_RESET 0x0001
75 #define LAN9303_SW_RESET_RESET BIT(0)
76 #define LAN9303_SW_IMR 0x0004
77 #define LAN9303_SW_IPR 0x0005
78 #define LAN9303_MAC_VER_ID_0 0x0400
79 #define LAN9303_MAC_RX_CFG_0 0x0401
81 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
82 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
83 #define LAN9303_MAC_RX_64_CNT_0 0x0411
84 #define LAN9303_MAC_RX_127_CNT_0 0x0412
85 #define LAN9303_MAC_RX_255_CNT_0 0x413
86 #define LAN9303_MAC_RX_511_CNT_0 0x0414
87 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
88 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
89 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
90 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
91 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
92 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
93 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
94 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
95 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
96 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
97 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
98 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
99 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
100 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
101 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
103 #define LAN9303_MAC_TX_CFG_0 0x0440
106 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
107 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
108 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
109 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
110 #define LAN9303_MAC_TX_64_CNT_0 0x0454
111 #define LAN9303_MAC_TX_127_CNT_0 0x0455
112 #define LAN9303_MAC_TX_255_CNT_0 0x0456
113 #define LAN9303_MAC_TX_511_CNT_0 0x0457
114 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
115 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
116 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
117 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
118 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
119 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
120 #define LAN9303_MAC_TX_LATECOL_0 0x045f
121 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
122 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
123 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
124 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
126 #define LAN9303_MAC_VER_ID_1 0x0800
127 #define LAN9303_MAC_RX_CFG_1 0x0801
128 #define LAN9303_MAC_TX_CFG_1 0x0840
129 #define LAN9303_MAC_VER_ID_2 0x0c00
130 #define LAN9303_MAC_RX_CFG_2 0x0c01
131 #define LAN9303_MAC_TX_CFG_2 0x0c40
132 #define LAN9303_SWE_ALR_CMD 0x1800
135 # define LAN9303_ALR_CMD_GET_NEXT      BIT(0)
136 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801
137 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802
144 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805
145 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806
146 #define LAN9303_SWE_ALR_CMD_STS 0x1808
147 # define ALR_STS_MAKE_PEND     BIT(0)
148 #define LAN9303_SWE_VLAN_CMD 0x180b
151 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
152 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
159 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
160 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
163 #define LAN9303_SWE_PORT_STATE 0x1843
164 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
167 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
170 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
172 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
174 #define LAN9303_SWE_PORT_MIRROR 0x1846
183 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
184 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0
185 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
187 #define LAN9303_BM_CFG 0x1c00
188 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
191 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
193 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
196 #define MII_LAN911X_SPECIAL_MODES 0x12
197 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
200 	regmap_reg_range(0x14, 0x17), /* misc, interrupt */
201 	regmap_reg_range(0x19, 0x19), /* endian test */
202 	regmap_reg_range(0x1d, 0x1d), /* hardware config */
203 	regmap_reg_range(0x23, 0x24), /* general purpose timer */
204 	regmap_reg_range(0x27, 0x27), /* counter */
205 	regmap_reg_range(0x29, 0x2a), /* PMI index regs */
206 	regmap_reg_range(0x68, 0x6a), /* flow control */
207 	regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
208 	regmap_reg_range(0x6d, 0x6f), /* misc */
209 	regmap_reg_range(0x70, 0x77), /* virtual phy */
210 	regmap_reg_range(0x78, 0x7a), /* GPIO */
211 	regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
212 	regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
216 	regmap_reg_range(0x00, 0x13),
217 	regmap_reg_range(0x18, 0x18),
218 	regmap_reg_range(0x1a, 0x1c),
219 	regmap_reg_range(0x1e, 0x22),
220 	regmap_reg_range(0x25, 0x26),
221 	regmap_reg_range(0x28, 0x28),
222 	regmap_reg_range(0x2b, 0x67),
223 	regmap_reg_range(0x7b, 0x7b),
224 	regmap_reg_range(0x7f, 0x7f),
225 	regmap_reg_range(0xb8, 0xff),
252 	for (i = 0; i < 5; i++) {  in lan9303_read()
255 			return 0;  in lan9303_read()
268 	for (i = 0; i < 25; i++) {  in lan9303_read_wait()
279 			return 0;  in lan9303_read_wait()
298 	return val & 0xffff;  in lan9303_virt_phy_reg_read()
345 	return val & 0xffff;  in lan9303_indirect_phy_read()
496 	 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the  in lan9303_detect_phy_setup()
499 	 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0  in lan9303_detect_phy_setup()
500 	 * and the IDs are 0-1-2, else it contains something different from  in lan9303_detect_phy_setup()
501 	 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.  in lan9303_detect_phy_setup()
502 	 * 0xffff is returned on MDIO read with no response.  in lan9303_detect_phy_setup()
505 	if (reg < 0) {  in lan9303_detect_phy_setup()
510 	chip->phy_addr_base = reg != 0 && reg != 0xffff;  in lan9303_detect_phy_setup()
513 		chip->phy_addr_base ? "1-2-3" : "0-1-2");  in lan9303_detect_phy_setup()
515 	return 0;  in lan9303_detect_phy_setup()
519 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
520 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
529 	for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)  in lan9303_alr_cache_find_free()
530 		if (entr->port_map == 0)  in lan9303_alr_cache_find_free()
546 	for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)  in lan9303_alr_cache_find_mac()
557 	for (i = 0; i < 25; i++) {  in lan9303_csr_reg_wait()
562 			return 0;  in lan9303_csr_reg_wait()
576 	lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);  in lan9303_alr_make_entry_raw()
578 	return 0;  in lan9303_alr_make_entry_raw()
586 	int ret = 0, i;  in lan9303_alr_loop()
591 	lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);  in lan9303_alr_loop()
612 		lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);  in lan9303_alr_loop()
621 	mac[0] = (dat0 >>  0) & 0xff;  in alr_reg_to_mac()
622 	mac[1] = (dat0 >>  8) & 0xff;  in alr_reg_to_mac()
623 	mac[2] = (dat0 >> 16) & 0xff;  in alr_reg_to_mac()
624 	mac[3] = (dat0 >> 24) & 0xff;  in alr_reg_to_mac()
625 	mac[4] = (dat1 >>  0) & 0xff;  in alr_reg_to_mac()
626 	mac[5] = (dat1 >>  8) & 0xff;  in alr_reg_to_mac()
640 	if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))  in alr_loop_cb_del_port_learned()
641 		return 0;  in alr_loop_cb_del_port_learned()
647 	return 0;  in alr_loop_cb_del_port_learned()
663 	if ((BIT(dump_ctx->port) & portmap) == 0)  in alr_loop_cb_fdb_port_dump()
664 		return 0;  in alr_loop_cb_fdb_port_dump()
668 	return dump_ctx->cb(mac, 0, is_static, dump_ctx->data);  in alr_loop_cb_fdb_port_dump()
689 	dat0 = 0;  in lan9303_alr_set_entry()
690 	dat0 |= (mac[0] << 0);  in lan9303_alr_set_entry()
695 	dat1 |= (mac[4] << 0);  in lan9303_alr_set_entry()
722 	return 0;  in lan9303_alr_add_port()
736 	if (entr->port_map == 0) /* zero means its free again */  in lan9303_alr_del_port()
742 	return 0;  in lan9303_alr_del_port()
781 /* forward special tagged packets from port 0 to port 1 *or* port 2 */
787 	 * for port 0  in lan9303_setup_tagging()
794 	/* tag incoming packets at port 1 and 2 on their way to port 0 to be  in lan9303_setup_tagging()
803  * - forward everything from port 1 to port 0
804  * - forward everything from port 2 to port 0
810 	lan9303_alr_del_port(chip, eth_stp_addr, 0);  in lan9303_separate_ports()
835 	lan9303_alr_add_port(chip, eth_stp_addr, 0, true);  in lan9303_bridge_ports()
845 	if (chip->reset_duration != 0)  in lan9303_handle_reset()
849 	gpiod_set_value_cansleep(chip->reset_gpio, 0);  in lan9303_handle_reset()
864 	return 0;  in lan9303_disable_processing()
894 		dev_err(chip->dev, "HW_CFG not ready: 0x%08x\n", reg);  in lan9303_check_device()
923 	dev_info(chip->dev, "Found LAN%4.4X rev. %u\n", (reg >> 16), reg & 0xffff);  in lan9303_check_device()
932 	return 0;  in lan9303_check_device()
950 	/* Make sure that port 0 is the cpu port */  in lan9303_setup()
951 	if (!dsa_is_cpu_port(ds, 0)) {  in lan9303_setup()
952 		dev_err(chip->dev, "port 0 is not the CPU port\n");  in lan9303_setup()
975 	ret = lan9303_enable_processing_port(chip, 0);  in lan9303_setup()
979 	/* Trap IGMP to port 0 */  in lan9303_setup()
982 					    LAN9303_SWE_GLB_INGR_IGMP_PORT(0),  in lan9303_setup()
988 	return 0;  in lan9303_setup()
1045 	for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++)  in lan9303_get_strings()
1055 	for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {  in lan9303_get_ethtool_stats()
1065 			reg = 0;  in lan9303_get_ethtool_stats()
1074 		return 0;  in lan9303_get_sset_count()
1084 	if (port == 0)  in lan9303_phy_read()
1098 	if (port == 0)  in lan9303_phy_write()
1113 		return 0;  in lan9303_port_enable()
1147 	return 0;  in lan9303_port_bridge_join()
1191 	portmask = 0x3 << (port * 2);  in lan9303_port_stp_state_set()
1233 	return 0;  in lan9303_port_fdb_del()
1260 		return 0;  in lan9303_port_mdb_prepare()
1264 	return 0;  in lan9303_port_mdb_prepare()
1295 	return 0;  in lan9303_port_mdb_del()
1308 	if (port == 0) {  in lan9303_phylink_get_caps()
1415 	chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1, 0);  in lan9303_register_switch()
1430 		return 0;  in lan9303_probe_reset_gpio()
1446 	return 0;  in lan9303_probe_reset_gpio()
1486 	return 0;  in lan9303_probe()
1495 	if (rc != 0)  in lan9303_remove()
1503 	return 0;  in lan9303_remove()