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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
37 #clock-cells = <0>;
47 #size-cells = <0>;
49 CPU0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
58 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
[all …]
H A Dqdu1000.dtsi26 #size-cells = <0>;
28 CPU0: cpu@0 {
31 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw 0>;
36 qcom,freq-domains = <&cpufreq_hw 0>;
54 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domains = <&cpufreq_hw 0>;
72 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsdx75.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
54 qcom,freq-domain = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
76 clocks = <&cpufreq_hw 0>;
80 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8188.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x000>;
50 reg = <0x100>;
68 reg = <0x200>;
86 reg = <0x300>;
104 reg = <0x400>;
122 reg = <0x500>;
140 reg = <0x600>;
158 reg = <0x700>;
[all …]
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]