Lines Matching +full:0 +full:x17200000
26 #size-cells = <0>;
28 CPU0: cpu@0 {
31 reg = <0x0 0x0>;
32 clocks = <&cpufreq_hw 0>;
36 qcom,freq-domains = <&cpufreq_hw 0>;
54 reg = <0x0 0x100>;
55 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domains = <&cpufreq_hw 0>;
72 reg = <0x0 0x200>;
73 clocks = <&cpufreq_hw 0>;
77 qcom,freq-domains = <&cpufreq_hw 0>;
90 reg = <0x0 0x300>;
91 clocks = <&cpufreq_hw 0>;
95 qcom,freq-domains = <&cpufreq_hw 0>;
129 CPU_OFF: cpu-sleep-0 {
134 arm,psci-suspend-param = <0x40000004>;
140 CLUSTER_SLEEP_0: cluster-sleep-0 {
145 arm,psci-suspend-param = <0x41000044>;
153 arm,psci-suspend-param = <0x41003344>;
163 mc_virt: interconnect-0 {
178 reg = <0x0 0x80000000 0x0 0x0>;
191 #power-domain-cells = <0>;
197 #power-domain-cells = <0>;
203 #power-domain-cells = <0>;
209 #power-domain-cells = <0>;
215 #power-domain-cells = <0>;
226 reg = <0x0 0x80000000 0x0 0x600000>;
231 reg = <0x0 0x80600000 0x0 0x40000>;
236 reg = <0x0 0x80640000 0x0 0x1c0000>;
241 reg = <0x0 0x80800000 0x0 0x60000>;
247 reg = <0x0 0x80860000 0x0 0x20000>;
252 reg = <0x0 0x80880000 0x0 0x20000>;
257 reg = <0x0 0x808a0000 0x0 0x40000>;
262 reg = <0x0 0x808e0000 0x0 0x4000>;
267 reg = <0x0 0x808e4000 0x0 0x10000>;
273 reg = <0x0 0x80900000 0x0 0x200000>;
279 reg = <0x0 0x80b00000 0x0 0x100000>;
284 reg = <0x0 0x80c00000 0x0 0x40000>;
289 reg = <0x0 0x81d00000 0x0 0x100000>;
294 reg = <0x0 0x81e00000 0x0 0x500000>;
299 reg = <0x0 0x82300000 0x0 0x500000>;
304 reg = <0x0 0x82800000 0x0 0xa00000>;
309 reg = <0x0 0x83200000 0x0 0x400000>;
314 reg = <0x0 0x83600000 0x0 0x400000>;
319 reg = <0x0 0x83a00000 0x0 0x400000>;
323 /* Linux kernel image is loaded at 0x83e00000 */
326 reg = <0x0 0x8be00000 0x0 0x10000>;
331 reg = <0x0 0x8be10000 0x0 0x14000>;
336 reg = <0x0 0x8c000000 0x0 0x12c00000>;
341 reg = <0x0 0x9ec00000 0x0 0x80000>;
346 reg = <0x0 0xa0000000 0x0 0x19600000>;
351 reg = <0x0 0xb9600000 0x0 0x6a00000>;
356 reg = <0x0 0xc0000000 0x0 0x3200000>;
361 reg = <0x0 0xc3200000 0x0 0x12c00000>;
366 soc: soc@0 {
370 ranges = <0 0 0 0 0x10 0>;
371 dma-ranges = <0 0 0 0 0x10 0>;
375 reg = <0x0 0x80000 0x0 0x1f4200>;
378 <0>,
379 <0>,
380 <0>;
388 reg = <0x0 0x00280000 0x0 0x31c00>;
402 reg = <0x0 0x900000 0x0 0x60000>;
416 dma-channel-mask = <0x3f>;
417 iommus = <&apps_smmu 0xf6 0x0>;
423 reg = <0x0 0x9c0000 0x0 0x2000>;
427 iommus = <&apps_smmu 0xe3 0x0>;
428 interconnects = <&clk_virt MASTER_QUP_CORE_0 0
429 &clk_virt SLAVE_QUP_CORE_0 0>;
439 reg = <0x0 0x980000 0x0 0x4000>;
442 pinctrl-0 = <&qup_uart0_default>;
450 reg = <0x0 0x984000 0x0 0x4000>;
454 pinctrl-0 = <&qup_i2c1_data_clk>;
457 #size-cells = <0>;
463 reg = <0x0 0x984000 0x0 0x4000>;
465 #size-cells = <0>;
469 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
476 reg = <0x0 0x988000 0x0 0x4000>;
480 pinctrl-0 = <&qup_i2c2_data_clk>;
483 #size-cells = <0>;
489 reg = <0x0 0x988000 0x0 0x4000>;
491 #size-cells = <0>;
495 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
502 reg = <0x0 0x98c000 0x0 0x4000>;
506 pinctrl-0 = <&qup_i2c3_data_clk>;
509 #size-cells = <0>;
515 reg = <0x0 0x98c000 0x0 0x4000>;
517 #size-cells = <0>;
521 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
528 reg = <0x0 0x990000 0x0 0x4000>;
532 pinctrl-0 = <&qup_i2c4_data_clk>;
535 #size-cells = <0>;
541 reg = <0x0 0x990000 0x0 0x4000>;
543 #size-cells = <0>;
547 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
554 reg = <0x0 0x994000 0x0 0x4000>;
558 pinctrl-0 = <&qup_i2c5_data_clk>;
561 #size-cells = <0>;
567 reg = <0x0 0x994000 0x0 0x4000>;
569 #size-cells = <0>;
573 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
580 reg = <0x0 0x998000 0x0 0x4000>;
584 pinctrl-0 = <&qup_i2c6_data_clk>;
587 #size-cells = <0>;
593 reg = <0x0 0x998000 0x0 0x4000>;
595 #size-cells = <0>;
599 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
606 reg = <0x0 0x99c000 0x0 0x4000>;
609 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
618 reg = <0x0 0xa00000 0x0 0x60000>;
632 dma-channel-mask = <0x3f>;
633 iommus = <&apps_smmu 0x116 0x0>;
639 reg = <0x0 0xac0000 0x0 0x2000>;
643 iommus = <&apps_smmu 0x103 0x0>;
651 reg = <0x0 0xa80000 0x0 0x4000>;
654 pinctrl-0 = <&qup_uart8_default>;
658 #size-cells = <0>;
664 reg = <0x0 0xa84000 0x0 0x4000>;
668 pinctrl-0 = <&qup_i2c9_data_clk>;
671 #size-cells = <0>;
677 reg = <0x0 0xa84000 0x0 0x4000>;
679 #size-cells = <0>;
683 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
690 reg = <0x0 0xa88000 0x0 0x4000>;
694 pinctrl-0 = <&qup_i2c10_data_clk>;
697 #size-cells = <0>;
703 reg = <0x0 0xa88000 0x0 0x4000>;
705 #size-cells = <0>;
709 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
716 reg = <0x0 0xa8c000 0x0 0x4000>;
720 pinctrl-0 = <&qup_i2c11_data_clk>;
723 #size-cells = <0>;
729 reg = <0x0 0xa8c000 0x0 0x4000>;
731 #size-cells = <0>;
735 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
742 reg = <0x0 0xa90000 0x0 0x4000>;
746 pinctrl-0 = <&qup_i2c12_data_clk>;
749 #size-cells = <0>;
755 reg = <0x0 0xa90000 0x0 0x4000>;
757 #size-cells = <0>;
761 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
768 reg = <0x0 0xa94000 0x0 0x4000>;
772 pinctrl-0 = <&qup_i2c13_data_clk>;
775 #size-cells = <0>;
781 reg = <0x0 0xa94000 0x0 0x4000>;
784 pinctrl-0 = <&qup_uart13_default>;
788 #size-cells = <0>;
794 reg = <0x0 0xa94000 0x0 0x4000>;
796 #size-cells = <0>;
800 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
807 reg = <0x0 0xa98000 0x0 0x4000>;
811 pinctrl-0 = <&qup_i2c14_data_clk>;
814 #size-cells = <0>;
820 reg = <0x0 0xa98000 0x0 0x4000>;
822 #size-cells = <0>;
826 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
833 reg = <0x0 0xa9c000 0x0 0x4000>;
837 pinctrl-0 = <&qup_i2c15_data_clk>;
840 #size-cells = <0>;
846 reg = <0x0 0xa9c000 0x0 0x4000>;
848 #size-cells = <0>;
852 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
860 reg = <0x0 0x1640000 0x0 0x45080>;
867 reg = <0x0 0x1f40000 0x0 0x20000>;
873 reg = <0x0 0x08804000 0x0 0x1000>,
874 <0x0 0x08805000 0x0 0x1000>;
890 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
891 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
896 iommus = <&apps_smmu 0x80 0x0>;
901 qcom,dll-config = <0x0007642c>;
902 qcom,ddr-config = <0x80040868>;
913 opp-avg-kBps = <400000 0>;
921 reg = <0x0 0x088e3000 0x0 0x120>;
922 #phy-cells = <0>;
934 reg = <0x0 0x088e5000 0x0 0x2000>;
950 #clock-cells = <0>;
953 #phy-cells = <0>;
960 reg = <0 0x0a6f8800 0 0x400>;
1006 reg = <0 0x0a600000 0 0xcd00>;
1009 iommus = <&apps_smmu 0xc0 0x0>;
1019 #size-cells = <0>;
1021 port@0 {
1022 reg = <0>;
1040 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
1041 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
1050 reg = <0x0 0xc400000 0x0 0x3000>,
1051 <0x0 0xc500000 0x0 0x400000>,
1052 <0x0 0xc440000 0x0 0x80000>,
1053 <0x0 0xc4c0000 0x0 0x10000>,
1054 <0x0 0xc42d000 0x0 0x4000>;
1058 qcom,ee = <0>;
1059 qcom,channel = <0>;
1061 #size-cells = <0>;
1068 reg = <0x0 0xf000000 0x0 0x1000000>;
1074 gpio-ranges = <&tlmm 0 0 151>;
1350 reg = <0 0x14680000 0 0x1000>;
1351 ranges = <0 0 0x14680000 0x1000>;
1357 reg = <0x94c 0xc8>;
1363 reg = <0x0 0x15000000 0x0 0x100000>;
1419 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
1420 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
1425 redistributor-stride = <0x0 0x20000>;
1430 reg = <0x0 0x17420000 0x0 0x1000>;
1433 ranges = <0x0 0x0 0x0 0x20000000>;
1436 reg = <0x17421000 0x1000>,
1437 <0x17422000 0x1000>;
1440 frame-number = <0>;
1444 reg = <0x17423000 0x1000>;
1451 reg = <0x17425000 0x1000>,
1452 <0x17426000 0x1000>;
1459 reg = <0x17427000 0x1000>;
1466 reg = <0x17429000 0x1000>;
1473 reg = <0x1742b000 0x1000>;
1480 reg = <0x1742d000 0x1000>;
1489 reg = <0x0 0x17a00000 0x0 0x10000>,
1490 <0x0 0x17a10000 0x0 0x10000>,
1491 <0x0 0x17a20000 0x0 0x10000>;
1492 reg-names = "drv-0", "drv-1", "drv-2";
1496 qcom,tcs-offset = <0xd00>;
1499 <WAKE_TCS 3>, <CONTROL_TCS 0>;
1567 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>;
1577 reg = <0x0 0x19100000 0x0 0xB8080>;
1584 reg = <0 0x19200000 0 0x80000>,
1585 <0 0x19300000 0 0x80000>,
1586 <0 0x19600000 0 0x80000>,
1587 <0 0x19700000 0 0x80000>,
1588 <0 0x19a00000 0 0x80000>,
1589 <0 0x19b00000 0 0x80000>,
1590 <0 0x19e00000 0 0x80000>,
1591 <0 0x19f00000 0 0x80000>,
1592 <0 0x1a200000 0 0x80000>;
1610 reg = <0 0x221c8000 0 0x1000>;
1615 reg = <0x12b 0x1>;
1616 bits = <0 2>;