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/linux/arch/arm/mach-mvebu/
H A Dkirkwood.h9 #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
10 #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
11 #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
13 #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
15 #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
16 #define CPU_CONFIG_ERROR_PROP 0x00000004
18 #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
19 #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
/linux/drivers/media/rc/keymaps/
H A Drc-nec-terratec-cinergy-xs.c18 { 0x1441, KEY_HOME},
19 { 0x1401, KEY_POWER2},
21 { 0x1442, KEY_MENU}, /* DVD menu */
22 { 0x1443, KEY_SUBTITLE},
23 { 0x1444, KEY_TEXT}, /* Teletext */
24 { 0x1445, KEY_DELETE},
26 { 0x1402, KEY_NUMERIC_1},
27 { 0x1403, KEY_NUMERIC_2},
28 { 0x1404, KEY_NUMERIC_3},
29 { 0x1405, KEY_NUMERIC_4},
[all …]
/linux/arch/mips/pic32/pic32mzda/
H A Dearly_pin.c10 #define PPS_BASE 0x1f800000
13 #define INT1R 0x1404
14 #define INT2R 0x1408
15 #define INT3R 0x140C
16 #define INT4R 0x1410
17 #define T2CKR 0x1418
18 #define T3CKR 0x141C
19 #define T4CKR 0x1420
20 #define T5CKR 0x1424
21 #define T6CKR 0x1428
[all …]
/linux/include/video/
H A Daty128.h13 #define CLOCK_CNTL_INDEX 0x0008
14 #define CLOCK_CNTL_DATA 0x000c
15 #define BIOS_0_SCRATCH 0x0010
16 #define BUS_CNTL 0x0030
17 #define BUS_CNTL1 0x0034
18 #define GEN_INT_CNTL 0x0040
19 #define CRTC_GEN_CNTL 0x0050
20 #define CRTC_EXT_CNTL 0x0054
21 #define DAC_CNTL 0x0058
22 #define I2C_CNTL_1 0x0094
[all …]
H A Dradeon.h6 #define RADEON_REGSIZE 0x4000
9 #define MM_INDEX 0x0000
10 #define MM_DATA 0x0004
11 #define BUS_CNTL 0x0030
12 #define HI_STAT 0x004C
13 #define BUS_CNTL1 0x0034
14 #define I2C_CNTL_1 0x0094
15 #define CNFG_CNTL 0x00E0
16 #define CNFG_MEMSIZE 0x00F8
17 #define CNFG_APER_0_BASE 0x0100
[all …]
/linux/drivers/phy/ti/
H A Dphy-am654-serdes.c23 #define CMU_R004 0x4
24 #define CMU_R060 0x60
25 #define CMU_R07C 0x7c
26 #define CMU_R088 0x88
27 #define CMU_R0D0 0xd0
28 #define CMU_R0E8 0xe8
30 #define LANE_R048 0x248
31 #define LANE_R058 0x258
32 #define LANE_R06c 0x26c
33 #define LANE_R070 0x270
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/linux/include/linux/mfd/mt6359/
H A Dregisters.h10 #define MT6359_SWCID 0xa
11 #define MT6359_TOPSTATUS 0x2a
12 #define MT6359_TOP_RST_MISC 0x14c
13 #define MT6359_MISC_TOP_INT_CON0 0x188
14 #define MT6359_MISC_TOP_INT_STATUS0 0x194
15 #define MT6359_TOP_INT_STATUS0 0x19e
16 #define MT6359_SCK_TOP_INT_CON0 0x528
17 #define MT6359_SCK_TOP_INT_STATUS0 0x534
18 #define MT6359_EOSC_CALI_CON0 0x53a
19 #define MT6359_EOSC_CALI_CON1 0x53c
[all …]
/linux/drivers/video/fbdev/kyro/
H A DSTG4000Reg.h54 NO_LUT = 0, RESERVED, GRAPHICS, OVERLAY
59 _8BPP = 0, _15BPP, _16BPP, _24BPP, _32BPP
64 GRAPHICS_MODE = 0, COLOR_KEY, PER_PIXEL_ALPHA, GLOBAL_ALPHA,
75 /* 0h */
76 volatile u32 Thread0Enable; /* 0x0000 */
77 volatile u32 Thread1Enable; /* 0x0004 */
78 volatile u32 Thread0Recover; /* 0x0008 */
79 volatile u32 Thread1Recover; /* 0x000C */
80 volatile u32 Thread0Step; /* 0x0010 */
81 volatile u32 Thread1Step; /* 0x0014 */
[all …]
/linux/drivers/net/ethernet/atheros/atlx/
H A Datlx.h23 #define SPEED_0 0xffff
30 #define MEDIA_TYPE_AUTO_SENSOR 0
33 #define REG_PM_CTRLSTAT 0x44
35 #define REG_PCIE_CAP_LIST 0x58
37 #define REG_VPD_CAP 0x6C
38 #define VPD_CAP_ID_MASK 0xFF
39 #define VPD_CAP_ID_SHIFT 0
40 #define VPD_CAP_NEXT_PTR_MASK 0xFF
42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF
44 #define VPD_CAP_VPD_FLAG 0x80000000
[all …]
/linux/drivers/net/dsa/sja1105/
H A Dsja1105_spi.c21 memset(buf, 0, size); in sja1105_spi_message_pack()
38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0}; in sja1105_xfer()
40 struct spi_transfer xfers[2] = {0}; in sja1105_xfer()
45 int rc, i = 0; in sja1105_xfer()
53 hdr_xfer = &xfers[0]; in sja1105_xfer()
56 for (i = 0; i < num_chunks; i++) { in sja1105_xfer()
67 msg.read_count = 0; in sja1105_xfer()
106 if (rc < 0) { in sja1105_xfer()
112 return 0; in sja1105_xfer()
139 sja1105_pack(packed_buf, value, 63, 0, 8); in sja1105_xfer_u64()
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp21_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
H A Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux/drivers/net/wireless/mediatek/mt7601u/
H A Dregs.h12 #define MT_ASIC_VERSION 0x0000
14 #define MT76XX_REV_E3 0x22
15 #define MT76XX_REV_E4 0x33
17 #define MT_CMB_CTRL 0x0020
21 #define MT_EFUSE_CTRL 0x0024
22 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
30 #define MT_EFUSE_DATA_BASE 0x0028
33 #define MT_COEXCFG0 0x0040
34 #define MT_COEXCFG0_COEX_EN BIT(0)
36 #define MT_WLAN_FUN_CTRL 0x0080
[all …]
/linux/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h41 #define REG_PM_CTRLSTAT 0x44
43 #define REG_PCIE_CAP_LIST 0x58
45 #define REG_DEVICE_CAP 0x5C
46 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
47 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
49 #define REG_DEVICE_CTRL 0x60
50 #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
52 #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
55 #define REG_VPD_CAP 0x6C
56 #define VPD_CAP_ID_MASK 0xff
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_4_1_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmCC_BIF_BX_FUSESTRAP0 0x14D7
31 #define mmBUS_CNTL 0x1508
32 #define mmCONFIG_CNTL 0x1509
33 #define mmCONFIG_MEMSIZE 0x150a
34 #define mmCONFIG_F0_BASE 0x150b
35 #define mmCONFIG_APER_SIZE 0x150c
36 #define mmCONFIG_REG_APER_SIZE 0x150d
[all …]
H A Dbif_5_0_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmCC_BIF_BX_FUSESTRAP0 0x14D7
31 #define mmCC_BIF_BX_STRAP2 0x152A
32 #define mmBIF_MM_INDACCESS_CNTL 0x1500
33 #define mmBIF_DOORBELL_APER_EN 0x1501
34 #define mmBUS_CNTL 0x1508
35 #define mmCONFIG_CNTL 0x1509
36 #define mmCONFIG_MEMSIZE 0x150a
[all …]
H A Dbif_5_1_d.h27 #define mmMM_INDEX 0x0
28 #define mmMM_INDEX_HI 0x6
29 #define mmMM_DATA 0x1
30 #define mmBIF_MM_INDACCESS_CNTL 0x1500
31 #define mmBUS_CNTL 0x1508
32 #define mmCONFIG_CNTL 0x1509
33 #define mmCONFIG_MEMSIZE 0x150a
34 #define mmCONFIG_F0_BASE 0x150b
35 #define mmCONFIG_APER_SIZE 0x150c
36 #define mmCONFIG_REG_APER_SIZE 0x150d
[all …]
/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/linux/drivers/net/ethernet/marvell/mvpp2/
H A Dmvpp2.h28 #define MVPP2_XDP_PASS 0
29 #define MVPP2_XDP_DROPPED BIT(0)
34 #define MVPP2_RX_DATA_FIFO_SIZE_REG(port) (0x00 + 4 * (port))
35 #define MVPP2_RX_ATTR_FIFO_SIZE_REG(port) (0x20 + 4 * (port))
36 #define MVPP2_RX_MIN_PKT_SIZE_REG 0x60
37 #define MVPP2_RX_FIFO_INIT_REG 0x64
38 #define MVPP22_TX_FIFO_THRESH_REG(port) (0x8840 + 4 * (port))
39 #define MVPP22_TX_FIFO_SIZE_REG(port) (0x8860 + 4 * (port))
42 #define MVPP2_RX_CTRL_REG(port) (0x140 + 4 * (port))
43 #define MVPP2_RX_LOW_LATENCY_PKT_SIZE(s) (((s) & 0xfff) << 16)
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/usb/storage/
H A Dunusual_devs.h56 UNUSUAL_DEV( 0x03eb, 0x2002, 0x0100, 0x0100,
63 UNUSUAL_DEV( 0x03ee, 0x6906, 0x0003, 0x0003,
69 UNUSUAL_DEV( 0x03f0, 0x0107, 0x0200, 0x0200,
72 USB_SC_8070, USB_PR_CB, NULL, 0),
75 UNUSUAL_DEV( 0x03f0, 0x070c, 0x0000, 0x0000,
85 UNUSUAL_DEV( 0x03f0, 0x4002, 0x0001, 0x0001,
90 UNUSUAL_DEV( 0x03f3, 0x0001, 0x0000, 0x9999,
101 UNUSUAL_DEV( 0x0409, 0x0040, 0x0000, 0x9999,
108 UNUSUAL_DEV( 0x040d, 0x6205, 0x0003, 0x0003,
119 UNUSUAL_DEV( 0x0411, 0x001c, 0x0113, 0x0113,
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_reg.h62 #define RADEON_MC_AGP_LOCATION 0x014c
63 #define RADEON_MC_AGP_START_MASK 0x0000FFFF
64 #define RADEON_MC_AGP_START_SHIFT 0
65 #define RADEON_MC_AGP_TOP_MASK 0xFFFF0000
67 #define RADEON_MC_FB_LOCATION 0x0148
68 #define RADEON_MC_FB_START_MASK 0x0000FFFF
69 #define RADEON_MC_FB_START_SHIFT 0
70 #define RADEON_MC_FB_TOP_MASK 0xFFFF0000
72 #define RADEON_AGP_BASE_2 0x015c /* r200+ only */
73 #define RADEON_AGP_BASE 0x0170
[all …]

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