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/linux/arch/sh/include/mach-common/mach/
H A Dsh7785lcr.h11 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
12 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
13 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
14 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
15 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
16 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
17 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
18 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
19 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
23 #define NOR_FLASH_ADDR 0x00000000
[all …]
H A Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
[all …]
/linux/arch/arm/mach-pxa/
H A Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
/linux/arch/sh/boards/
H A Dboard-urquell.c32 * SW2 0x1x xxxx -> little endian
39 * 0x00000000 - 0x04000000 (CS0) Nor Flash
40 * 0x04000000 - 0x04200000 (CS1) SRAM
41 * 0x05000000 - 0x05800000 (CS1) on board register
42 * 0x05800000 - 0x06000000 (CS1) LAN91C111
43 * 0x06000000 - 0x06400000 (CS1) PCMCIA
44 * 0x08000000 - 0x10000000 (CS2-CS3) DDR3
45 * 0x10000000 - 0x14000000 (CS4) PCIe
46 * 0x14000000 - 0x14800000 (CS5) Core0 LRAM/URAM
47 * 0x14800000 - 0x15000000 (CS5) Core1 LRAM/URAM
[all …]
/linux/arch/sh/include/cpu-sh4/cpu/
H A Daddrspace.h10 #define P0SEG 0x00000000
11 #define P1SEG 0x80000000
12 #define P2SEG 0xa0000000
13 #define P3SEG 0xc0000000
14 #define P4SEG 0xe0000000
18 #define P4SEG_IC_ADDR 0xf0000000
19 #define P4SEG_IC_DATA 0xf1000000
20 #define P4SEG_ITLB_ADDR 0xf2000000
21 #define P4SEG_ITLB_DATA 0xf3000000
22 #define P4SEG_OC_ADDR 0xf4000000
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dhisilicon,fmc-spi-nor.txt7 - size-cells : Should be 0.
16 #size-cells = <0>;
17 reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
20 flash@0 {
22 reg = <0>;
H A Dnxp-spifi.txt5 mode 0 or 3. The controller operates in either command or memory
25 - spi-cpol : Controller only supports mode 0 and 3 so either
37 reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
44 flash@0 {
52 partition@0 {
54 reg = <0 0x200000>;
/linux/drivers/input/serio/
H A Di8042-snirm.h26 #define I8042_COMMAND_REG (kbd_iobase + 0x64UL)
27 #define I8042_DATA_REG (kbd_iobase + 0x60UL)
31 return readb(kbd_iobase + 0x60UL); in i8042_read_data()
36 return readb(kbd_iobase + 0x64UL); in i8042_read_status()
41 writeb(val, kbd_iobase + 0x60UL); in i8042_write_data()
46 writeb(val, kbd_iobase + 0x64UL); in i8042_write_command()
52 kbd_iobase = ioremap(0x16000000, 4); in i8042_platform_init()
56 kbd_iobase = ioremap(0x14000000, 4); in i8042_platform_init()
63 return 0; in i8042_platform_init()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/fuc/
H A Dmacros.fuc25 #define GT215 0xa3
26 #define GF100 0xc0
27 #define GF119 0xd9
28 #define GK208 0x108
33 #define NV_PPWR_INTR_TRIGGER 0x0000
34 #define NV_PPWR_INTR_TRIGGER_USER1 0x00000080
35 #define NV_PPWR_INTR_TRIGGER_USER0 0x00000040
36 #define NV_PPWR_INTR_ACK 0x0004
37 #define NV_PPWR_INTR_ACK_SUBINTR 0x00000800
38 #define NV_PPWR_INTR_ACK_WATCHDOG 0x00000002
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,versatile-fpga-irq.txt18 the interrupts are valid. Unconnected/unused lines are set to 0, and
30 reg = <0x14000000 0x100>;
31 clear-mask = <0xffffffff>;
32 valid-mask = <0x003fffff>;
/linux/arch/sh/include/mach-se/mach/
H A Dse7751.h19 #define PA_ROM 0x00000000 /* EPROM */
20 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
21 #define PA_FROM 0x01000000 /* EPROM */
22 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
23 #define PA_EXT1 0x04000000
24 #define PA_EXT1_SIZE 0x04000000
25 #define PA_EXT2 0x08000000
26 #define PA_EXT2_SIZE 0x04000000
27 #define PA_SDRAM 0x0c000000
28 #define PA_SDRAM_SIZE 0x04000000
[all …]
H A Dse.h16 #define PA_ROM 0x00000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0x01000000 /* EPROM */
19 #define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */
20 #define PA_EXT1 0x04000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_EXT2 0x08000000
23 #define PA_EXT2_SIZE 0x04000000
24 #define PA_SDRAM 0x0c000000
25 #define PA_SDRAM_SIZE 0x04000000
[all …]
H A Dse7343.h16 /* Area 0 */
17 #define PA_ROM 0x00000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */
19 #define PA_FROM 0x00400000 /* Flash ROM */
20 #define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */
21 #define PA_SRAM 0x00800000 /* SRAM */
22 #define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */
24 #define PA_EXT1 0x04000000
25 #define PA_EXT1_SIZE 0x04000000
27 #define PA_EXT2 0x08000000
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg_8xx.h29 #define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */
30 #define SPRN_NRI 82 /* Non recoverable interrupt (EE=0, RI=0) */
38 #define LCTRL1_CTE_GT 0xc0000000
39 #define LCTRL1_CTF_LT 0x14000000
40 #define LCTRL1_CRWE_RW 0x00000000
41 #define LCTRL1_CRWE_RO 0x00040000
42 #define LCTRL1_CRWE_WO 0x000c0000
43 #define LCTRL1_CRWF_RW 0x00000000
44 #define LCTRL1_CRWF_RO 0x00010000
45 #define LCTRL1_CRWF_WO 0x00030000
[all …]
/linux/arch/powerpc/boot/
H A Dwii.c22 #define EXI_CTRL HW_REG(0x0d800070)
23 #define EXI_CTRL_ENABLE (1<<0)
25 #define MEM2_TOP (0x10000000 + 64*1024*1024)
42 if (pa < 0x10000000 || pa > 0x14000000) in mipc_check_address()
44 return 0; in mipc_check_address()
52 hdrp = (struct mipc_infohdr **)0x13fffffc; in mipc_get_infohdr()
93 error = 0; in mipc_get_mem2_boundary()
/linux/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h19 #define AR71XX_APB_BASE 0x18000000
20 #define AR71XX_GE0_BASE 0x19000000
21 #define AR71XX_GE0_SIZE 0x10000
22 #define AR71XX_GE1_BASE 0x1a000000
23 #define AR71XX_GE1_SIZE 0x10000
24 #define AR71XX_EHCI_BASE 0x1b000000
25 #define AR71XX_EHCI_SIZE 0x1000
26 #define AR71XX_OHCI_BASE 0x1c000000
27 #define AR71XX_OHCI_SIZE 0x1000
28 #define AR71XX_SPI_BASE 0x1f000000
[all …]
/linux/arch/mips/include/asm/ip32/
H A Dcrime.h18 #define CRIME_BASE 0x14000000 /* physical */
22 #define CRIME_ID_MASK 0xff
23 #define CRIME_ID_IDBITS 0xf0
24 #define CRIME_ID_IDVALUE 0xa0
25 #define CRIME_ID_REV 0x0f
26 #define CRIME_REV_PETTY 0x00
27 #define CRIME_REV_11 0x11
28 #define CRIME_REV_13 0x13
29 #define CRIME_REV_14 0x14
32 #define CRIME_CONTROL_MASK 0x3fff
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi22 reg = <0 0x10000000 0 0x1000>;
28 reg = <0 0x10001000 0 0x1000>;
34 reg = <0 0x10018000 0 0x710>;
40 reg = <0 0x10006000 0 0x1000>;
45 #size-cells = <0>;
53 #power-domain-cells = <0>;
62 #power-domain-cells = <0>;
69 #power-domain-cells = <0>;
78 #size-cells = <0>;
85 #size-cells = <0>;
[all …]
/linux/arch/mips/boot/dts/img/
H A Dboston.dts24 #size-cells = <0>;
26 cpu@0 {
29 reg = <0>;
34 memory@0 {
36 reg = <0x00000000 0x10000000>;
42 reg = <0x10000000 0x2000000>;
51 ranges = <0x02000000 0 0x40000000
52 0x40000000 0 0x40000000>;
54 bus-range = <0x00 0xff>;
56 interrupt-map-mask = <0 0 0 7>;
[all …]
/linux/drivers/parisc/
H A Dpower.c36 #define DIAG_CODE(code) (0x14000000 + ((code)<<5))
39 (DIAG_CODE(code) + ((rDiagReg)<<21) + ((t_ch)<<16) + ((t_th)<<0) )
41 #define MTCPU(dr, gr) MFCPU_X(dr, gr, 0, 0x12) /* move value of gr to dr[dr] */
42 #define MFCPU_C(dr, gr) MFCPU_X(dr, gr, 0, 0x30) /* for dr0 and dr8 only ! */
43 #define MFCPU_T(dr, gr) MFCPU_X(dr, 0, gr, 0xa0) /* all dr except dr0 and dr8 */
59 if (shutdown_timer == 0) in process_shutdown()
110 button_not_pressed = (gsc_readl(soft_power_reg) & 0x1); in kpowerswd()
114 * the power switch status is stored in Bit 0 ("the highest bit") in kpowerswd()
119 button_not_pressed = (__getDIAG(25) & 0x80000000); in kpowerswd()
125 shutdown_timer = 0; in kpowerswd()
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8.dtsi12 /memreserve/ 0x80000000 0x00010000;
34 #size-cells = <0>;
36 cpu0: cpu@0 {
39 reg = <0x0 0x0>;
45 reg = <0x0 0x1>;
51 reg = <0x0 0x2>;
57 reg = <0x0 0x3>;
70 reg = <0x00000000 0x80000000 0 0x80000000>,
71 <0x00000008 0x80000000 0 0x80000000>;
98 reg = <0x0 0x2a440000 0 0x1000>,
[all …]
/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
90 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]

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