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/freebsd/sys/dev/clk/allwinner/
H A Dccu_h6_r.c55 CCU_RESET(RST_R_APB1_TIMER, 0x11c, 16)
56 CCU_RESET(RST_R_APB1_TWD, 0x12c, 16)
57 CCU_RESET(RST_R_APB1_PWM, 0x13c, 16)
58 CCU_RESET(RST_R_APB2_UART, 0x18c, 16)
59 CCU_RESET(RST_R_APB2_I2C, 0x19c, 16)
60 CCU_RESET(RST_R_APB1_IR, 0x1cc, 16)
61 CCU_RESET(RST_R_APB1_W1, 0x1ec, 16)
65 CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0)
66 CCU_GATE(CLK_R_APB1_TWD, "r_apb1-twd", "r_apb1", 0x12c, 0)
67 CCU_GATE(CLK_R_APB1_PWM, "r_apb1-pwm", "r_apb1", 0x13c, 0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx51-pinfunc.h13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0
14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0
15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0
16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0
17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0
18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0
19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0
20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0
21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0
22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey-pinctrl.dtsi12 pinctrl-0 = <
22 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
28 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
29 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
30 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
31 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
32 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
33 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
34 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
35 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_dev_err.h10 #define ADF_ERRSOU0 (0x3A000 + 0x00)
11 #define ADF_ERRSOU1 (0x3A000 + 0x04)
12 #define ADF_ERRSOU2 (0x3A000 + 0x08)
13 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
14 #define ADF_ERRSOU4 (0x3A000 + 0xD0)
15 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
16 #define ADF_ERRMSK0 (0x3A000 + 0x10)
17 #define ADF_ERRMSK1 (0x3A000 + 0x14)
18 #define ADF_ERRMSK2 (0x3A000 + 0x18)
19 #define ADF_ERRMSK3 (0x3A000 + 0x1C)
[all …]
/freebsd/sys/arm/ti/
H A Dti_spireg.h32 #define MCSPI_REVISION 0x0
34 #define MCSPI_REVISION_SCHEME_MSK 0x3
36 #define MCSPI_REVISION_FUNC_MSK 0xfff
38 #define MCSPI_REVISION_RTL_MSK 0x1f
40 #define MCSPI_REVISION_MAJOR_MSK 0x7
42 #define MCSPI_REVISION_CUSTOM_MSK 0x3
43 #define MCSPI_REVISION_MINOR_SHIFT 0
44 #define MCSPI_REVISION_MINOR_MSK 0x3f
45 #define MCSPI_SYSCONFIG 0x110
47 #define MCSPI_SYSSTATUS 0x114
[all …]
/freebsd/tools/test/stress2/misc/
H A Dsyzkaller40.sh7 # db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe01aaec6880
8 # vpanic() at vpanic+0x181/frame 0xfffffe01aaec68d0
9 # panic() at panic+0x43/frame 0xfffffe01aaec6930
10 # __mtx_lock_flags() at __mtx_lock_flags+0x13c/frame 0xfffffe01aaec6980
11 # soo_aio_cancel() at soo_aio_cancel+0x51/frame 0xfffffe01aaec69b0
12 # aio_cancel_job() at aio_cancel_job+0x95/frame 0xfffffe01aaec69f0
13 # aio_proc_rundown() at aio_proc_rundown+0xcf/frame 0xfffffe01aaec6a40
14 # exit1() at exit1+0x36e/frame 0xfffffe01aaec6ab0
15 # sys_sys_exit() at sys_sys_exit+0xd/frame 0xfffffe01aaec6ac0
16 # amd64_syscall() at amd64_syscall+0x147/frame 0xfffffe01aaec6bf0
[all …]
H A Daltbufferflushes.sh35 # Stopped at kdb_enter+0x2b: nop
37 # Tracing pid 2526 tid 100070 td 0xc46f8360
38 # kdb_enter(c094247f) at kdb_enter+0x2b
39 # panic(c09402b6,c46f8360,0,12,c06af5d9,...) at panic+0x14b
40 # _lockmgr(d864a748,202122,c479f788,c46f8360,c094b01c,12d) at _lockmgr+0x41a
41 # getblk(c479f6b8,5d51940,0,4000,0,...) at getblk+0x13c
42 # breadn(c479f6b8,5d51940,0,4000,0,...) at breadn+0x2f
43 # bread(c479f6b8,5d51940,0,4000,0,e6d13544,c4743eac,0,c095a185,56d) at bread+0x20
44 # ffs_alloccg(c47408c4,104,1754628,0,4000,c4743eac,1,c095a185,4d8) at ffs_alloccg+0x11d
45 # ffs_hashalloc(c47408c4,104,1754628,0,4000,...) at ffs_hashalloc+0x45
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_eeprom.h13 MT_EE_CHIP_ID = 0x000,
14 MT_EE_VERSION = 0x002,
15 MT_EE_MAC_ADDR = 0x004,
16 MT_EE_PCI_ID = 0x00A,
17 MT_EE_ANTENNA = 0x022,
18 MT_EE_CFG1_INIT = 0x024,
19 MT_EE_NIC_CONF_0 = 0x034,
20 MT_EE_NIC_CONF_1 = 0x036,
21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,
22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,
[all …]
/freebsd/sys/dev/xilinx/
H A Dxlnx_pcib.h36 #define XLNX_PCIE_VSEC 0x12c
37 #define XLNX_PCIE_BIR 0x130 /* Bridge Info Register */
38 #define XLNX_PCIE_BSCR 0x134 /* Bridge Status and Control */
39 #define XLNX_PCIE_IDR 0x138 /* Interrupt Decode Register */
40 #define XLNX_PCIE_IMR 0x13C /* Interrupt Mask Register */
41 #define IMR_LINK_DOWN (1 << 0)
44 #define IMR_CFG_COMPL_STATUS_M (0x7 << IMR_CFG_COMPL_STATUS_S)
59 #define XLNX_PCIE_BLR 0x140 /* Bus Location Register */
60 #define XLNX_PCIE_PHYSCR 0x144 /* PHY Status/Control Register */
62 #define XLNX_PCIE_RPSCR 0x148 /* Root Port Status/Control Register */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/imx/
H A Dfsl,imx8qxp-dc-blit-engine.yaml56 (4:4:4, 4:2:2, 4:2:0).
82 "^blitblend@[0-9a-f]+$":
90 "^clut@[0-9a-f]+$":
98 "^fetchdecode@[0-9a-f]+$":
106 "^fetcheco@[0-9a-f]+$":
114 "^fetchwarp@[0-9a-f]+$":
122 "^filter@[0-9a-f]+$":
130 "^hscaler@[0-9a-f]+$":
138 "^matrix@[0-9a-f]+$":
146 "^rop@[0-9a-f]+$":
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7915/
H A Dregs.h130 #define MT_MCU_WFDMA0_BASE 0x2000
133 #define MT_MCU_WFDMA0_DUMMY_CR MT_MCU_WFDMA0(0x120)
136 #define MT_MCU_WFDMA1_BASE 0x3000
140 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
146 #define MT_PLE_BASE 0x820c0000
149 #define MT_PLE_HOST_RPT0 MT_PLE(0x030)
154 #define MT_FL_Q2_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0x8)
155 #define MT_FL_Q3_CTRL MT_PLE(__OFFS(PLE_FL_Q_CTRL) + 0xc)
165 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
167 #define MT_PSE_BASE 0x820c8000
[all …]
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm7435.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
43 #address-cells = <0>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
69 ranges = <0 0x10000000 0x01000000>;
73 reg = <0x41b500 0x40>, <0x41b600 0x40>,
74 <0x41b700 0x40>, <0x41b800 0x40>;
85 reg = <0x403000 0x30>;
[all …]
H A Dbcm7425.dtsi9 #size-cells = <0>;
13 cpu@0 {
16 reg = <0>;
31 #address-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
57 ranges = <0 0x10000000 0x01000000>;
61 reg = <0x41a400 0x30>, <0x41a600 0x30>;
72 reg = <0x403000 0x30>;
81 reg = <0x400000 0xdc>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-var-om44customboard.dtsi16 pinctrl-0 = <&gpio_led_pins>;
33 pinctrl-0 = <&gpio_key_pins>;
35 #size-cells = <0>;
48 pinctrl-0 = <&hdmi_hpd_pins>;
65 OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */
66 OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */
67 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */
68 OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */
74 OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
75 OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-evm-gesi-exp-board.dtso31 pinctrl-0 = <&rgmii1_default_pins
72 pinctrl-0 = <&mdio0_default_pins>;
75 #size-cells = <0>;
77 cpsw9g_phy0: ethernet-phy@0 {
78 reg = <0>;
124 J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
125 J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
131 J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */
132 J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */
133 J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */
[all …]

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