Searched +full:0 +full:x13200 (Results 1 – 4 of 4) sorted by relevance
| /linux/arch/x86/platform/ce4100/ |
| H A D | falconfalls.dts | 16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
26 soc@0 {
36 reg = <0xfec00000 0x1000>;
41 reg = <0xfed00000 0x200>;
46 reg = <0xfee00000 0x1000>;
54 bus-range = <0 0>;
55 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
56 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
[all …]
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| /linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-37xx.dtsi | 33 reg = <0 0x4000000 0 0x200000>;
38 reg = <0 0x4400000 0 0x1000000>;
45 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0>;
83 /* 32M internal register @ 0xd000_0000 */
84 ranges = <0x0 0x0 0xd0000000 0x2000000>;
88 reg = <0x8300 0x40>;
96 reg = <0xd000 0x1000>;
102 #size-cells = <0>;
[all …]
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_gt_mcr.c | 49 #define STEER_SEMAPHORE XE_REG(0xFD0)
62 { 0x00B100, 0x00B3FF },
67 { 0x008C80, 0x008CFF },
68 { 0x00B100, 0x00B3FF },
78 { 0x00DD00, 0x00DDFF },
79 { 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
84 { 0x00B000, 0x00B0FF },
85 { 0x00D880, 0x00D8FF },
90 * We have several types of MCR registers where steering to (0,0) will always
95 { 0x004000, 0x004AFF }, /* HALF-BSLICE */
[all …]
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| /linux/drivers/gpu/drm/msm/disp/mdp5/ |
| H A D | mdp5_cfg.c | 22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
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