49 #define STEER_SEMAPHORE		XE_REG(0xFD0)
62 	{ 0x00B100, 0x00B3FF },
67 	{ 0x008C80, 0x008CFF },
68 	{ 0x00B100, 0x00B3FF },
78 	{ 0x00DD00, 0x00DDFF },
79 	{ 0x00E900, 0x00FFFF }, /* 0xEA00 - OxEFFF is unused */
84 	{ 0x00B000, 0x00B0FF },
85 	{ 0x00D880, 0x00D8FF },
90  * We have several types of MCR registers where steering to (0,0) will always
95 	{ 0x004000, 0x004AFF },		/* HALF-BSLICE */
96 	{ 0x008800, 0x00887F },		/* CC */
97 	{ 0x008A80, 0x008AFF },		/* TILEPSMI */
98 	{ 0x00B000, 0x00B0FF },		/* HALF-BSLICE */
99 	{ 0x00B100, 0x00B3FF },		/* L3BANK */
100 	{ 0x00C800, 0x00CFFF },		/* HALF-BSLICE */
101 	{ 0x00D800, 0x00D8FF },		/* HALF-BSLICE */
102 	{ 0x00DD00, 0x00DDFF },		/* BSLICE */
103 	{ 0x00E900, 0x00E9FF },		/* HALF-BSLICE */
104 	{ 0x00EC00, 0x00EEFF },		/* HALF-BSLICE */
105 	{ 0x00F000, 0x00FFFF },		/* HALF-BSLICE */
106 	{ 0x024180, 0x0241FF },		/* HALF-BSLICE */
111 	{ 0x000B00, 0x000BFF },         /* SQIDI */
112 	{ 0x001000, 0x001FFF },         /* SQIDI */
113 	{ 0x004000, 0x0048FF },         /* GAM */
114 	{ 0x008700, 0x0087FF },         /* SQIDI */
115 	{ 0x00B000, 0x00B0FF },         /* NODE */
116 	{ 0x00C800, 0x00CFFF },         /* GAM */
117 	{ 0x00D880, 0x00D8FF },         /* NODE */
118 	{ 0x00DD00, 0x00DDFF },         /* OAAL2 */
123 	{ 0x00B100, 0x00B3FF },
128 	{ 0x008150, 0x00815F },
129 	{ 0x009520, 0x00955F },
130 	{ 0x00DE80, 0x00E8FF },
131 	{ 0x024A00, 0x024A7F },
137 	{ 0x005200, 0x0052FF },		/* GSLICE */
138 	{ 0x005400, 0x007FFF },		/* GSLICE */
139 	{ 0x008140, 0x00815F },		/* GSLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
140 	{ 0x008D00, 0x008DFF },		/* DSS */
141 	{ 0x0094D0, 0x00955F },		/* GSLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
142 	{ 0x009680, 0x0096FF },		/* DSS */
143 	{ 0x00D800, 0x00D87F },		/* GSLICE */
144 	{ 0x00DC00, 0x00DCFF },		/* GSLICE */
145 	{ 0x00DE80, 0x00E8FF },		/* DSS (0xE000-0xE0FF reserved ) */
146 	{ 0x017000, 0x017FFF },		/* GSLICE */
147 	{ 0x024A00, 0x024A7F },		/* DSS */
153 	{ 0x008140, 0x00817F },		/* COMPUTE (0x8140-0x814F & 0x8160-0x817F), DSS (0x8150-0x815F) */
154 	{ 0x0094D0, 0x00955F },		/* COMPUTE (0x94D0-0x951F), DSS (0x9520-0x955F) */
155 	{ 0x009680, 0x0096FF },		/* DSS */
156 	{ 0x00DC00, 0x00DCFF },		/* COMPUTE */
157 	{ 0x00DE80, 0x00E7FF },		/* DSS (0xDF00-0xE1FF reserved ) */
163 	{ 0x005200, 0x0052FF },		/* SLICE */
164 	{ 0x005500, 0x007FFF },		/* SLICE */
165 	{ 0x008140, 0x00815F },		/* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
166 	{ 0x0094D0, 0x00955F },		/* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
167 	{ 0x009680, 0x0096FF },		/* DSS */
168 	{ 0x00D800, 0x00D87F },		/* SLICE */
169 	{ 0x00DC00, 0x00DCFF },		/* SLICE */
170 	{ 0x00DE80, 0x00E8FF },		/* DSS (0xE000-0xE0FF reserved) */
175 	{ 0x393200, 0x39323F },
176 	{ 0x393400, 0x3934FF },
181 	{ 0x000B00, 0x000BFF },		/* SF (SQIDI replication) */
182 	{ 0x001000, 0x001FFF },		/* SF (SQIDI replication) */
183 	{ 0x004000, 0x004AFF },		/* GAM (MSLICE replication) */
184 	{ 0x008700, 0x0087FF },		/* MCFG (SQIDI replication) */
185 	{ 0x00C800, 0x00CFFF },		/* GAM (MSLICE replication) */
186 	{ 0x00F000, 0x00FFFF },		/* GAM (MSLICE replication) */
191 	{ 0x005200, 0x0052FF },         /* SLICE */
192 	{ 0x005500, 0x007FFF },         /* SLICE */
193 	{ 0x008140, 0x00815F },         /* SLICE (0x8140-0x814F), DSS (0x8150-0x815F) */
194 	{ 0x0094D0, 0x00955F },         /* SLICE (0x94D0-0x951F), DSS (0x9520-0x955F) */
195 	{ 0x009680, 0x0096FF },         /* DSS */
196 	{ 0x00D800, 0x00D87F },         /* SLICE */
197 	{ 0x00DC00, 0x00DCFF },         /* SLICE */
198 	{ 0x00DE80, 0x00E8FF },         /* DSS (0xE000-0xE0FF reserved) */
199 	{ 0x00E980, 0x00E9FF },         /* SLICE */
200 	{ 0x013000, 0x0133FF },         /* DSS (0x13000-0x131FF), SLICE (0x13200-0x133FF) */
205 	{ 0x000B00, 0x000BFF },
206 	{ 0x001000, 0x001FFF },
211 	{ 0x004000, 0x004AFF },         /* GAM, rsvd, GAMWKR */
212 	{ 0x008700, 0x00887F },         /* SQIDI, MEMPIPE */
213 	{ 0x00B000, 0x00B3FF },         /* NODE, L3BANK */
214 	{ 0x00C800, 0x00CFFF },         /* GAM */
215 	{ 0x00D880, 0x00D8FF },         /* NODE */
216 	{ 0x00DD00, 0x00DDFF },         /* MEMPIPE */
217 	{ 0x00E900, 0x00E97F },         /* MEMPIPE */
218 	{ 0x00F000, 0x00FFFF },         /* GAM, GAMWKR */
219 	{ 0x013400, 0x0135FF },         /* MEMPIPE */
224 	{ 0x388160, 0x38817F },
225 	{ 0x389480, 0x3894CF },
230 	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
231 	{ 0x384900, 0x384AFF },         /* GAM */
232 	{ 0x389560, 0x3895FF },         /* MEDIAINF */
233 	{ 0x38B600, 0x38B8FF },         /* L3BANK */
234 	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
235 	{ 0x38F000, 0x38F0FF },         /* GAM */
236 	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
241 	{ 0x384000, 0x3847DF },         /* GAM, rsvd, GAM */
242 	{ 0x384900, 0x384AFF },         /* GAM */
243 	{ 0x389560, 0x3895FF },         /* MEDIAINF */
244 	{ 0x38B600, 0x38B8FF },         /* L3BANK */
245 	{ 0x38C800, 0x38D07F },         /* GAM, MEDIAINF */
246 	{ 0x38D0D0, 0x38F0FF },		/* MEDIAINF, GAM */
247 	{ 0x393C00, 0x393C7F },         /* MEDIAINF */
263 		 * Bank 0 is always valid _except_ when the bank mask is 010b.  in init_steering_l3bank()
267 			bank_mask & BIT(0) ? 0 : 2;  in init_steering_l3bank()
278 		gt->steering[L3BANK].group_target = (bank >> 2) & 0x7;  in init_steering_l3bank()
279 		gt->steering[L3BANK].instance_target = bank & 0x3;  in init_steering_l3bank()
284 		gt->steering[L3BANK].group_target = 0;	/* unused */  in init_steering_l3bank()
302 	gt->steering[MSLICE].instance_target = 0;	/* unused */  in init_steering_mslice()
307 	 * so we just always pick LNCF 0 here.  in init_steering_mslice()
310 	gt->steering[LNCF].instance_target = 0;		/* unused */  in init_steering_mslice()
316 	u32 max_slices = 0, max_subslices = 0;  in dss_per_group()
333 	if (ret < 0 || max_slices == 0)  in dss_per_group()
338 	if (ret < 0 || max_subslices == 0)  in dss_per_group()
393 				   min(xe_dss_mask_group_ffs(gt->fuse_topo.g_dss_mask, 0, 0),  in init_steering_dss()
394 				       xe_dss_mask_group_ffs(gt->fuse_topo.c_dss_mask, 0, 0)),  in init_steering_dss()
406 		gt->steering[OADDRM].group_target = 0;  in init_steering_oaddrm()
410 	gt->steering[OADDRM].instance_target = 0;	/* unused */  in init_steering_oaddrm()
420 	gt->steering[SQIDI_PSMI].instance_target = select & 0x1;  in init_steering_sqidi_psmi()
433 	[INSTANCE0] =	{ "INSTANCE 0",	NULL },
494 	/* Mark instance 0 as initialized, we need this early for VRAM and CCS probe. */  in xe_gt_mcr_init_early()
510 	for (int i = 0; i < NUM_STEERING_TYPES; i++) {  in xe_gt_mcr_init()
533 		u32 steer_val = REG_FIELD_PREP(MCR_SLICE_MASK, 0) |  in xe_gt_mcr_set_implicit_defaults()
570 	for (int type = 0; type < IMPLICIT_STEERING; type++) {  in xe_gt_mcr_get_nonterminated_steering()
574 		for (int i = 0; gt->steering[type].ranges[i].end > 0; i++) {  in xe_gt_mcr_get_nonterminated_steering()
589 		for (int i = 0; implicit_ranges[i].end > 0; i++)  in xe_gt_mcr_get_nonterminated_steering()
595 	 * steering. Just steer to 0/0 as a guess and raise a warning.  in xe_gt_mcr_get_nonterminated_steering()
600 	*group = 0;  in xe_gt_mcr_get_nonterminated_steering()
601 	*instance = 0;  in xe_gt_mcr_get_nonterminated_steering()
614 	int ret = 0;  in mcr_lock()
625 		ret = xe_mmio_wait32(&gt->mmio, STEER_SEMAPHORE, 0x1, 0x1, 10, NULL,  in mcr_lock()
635 		xe_mmio_write32(&gt->mmio, STEER_SEMAPHORE, 0x1);  in mcr_unlock()
651 	u32 steer_val, val = 0;  in rw_with_mcr_steering()
728 					   group, instance, 0);  in xe_gt_mcr_unicast_read_any()
756 	val = rw_with_mcr_steering(gt, reg_mcr, MCR_OP_READ, group, instance, 0);  in xe_gt_mcr_unicast_read()
810 	for (int i = 0; i < NUM_STEERING_TYPES; i++) {  in xe_gt_mcr_steering_dump()
816 			for (int j = 0; gt->steering[i].ranges[j].end; j++)  in xe_gt_mcr_steering_dump()
817 				drm_printf(p, "\t0x%06x - 0x%06x\n",  in xe_gt_mcr_steering_dump()