Searched +full:0 +full:x12fc (Results 1 – 19 of 19) sorted by relevance
15 cpu: cpu@0 {40 opp-supported-hw = <0xffffffff 3>;46 opp-supported-hw = <0xffffffff 3>;53 opp-supported-hw = <0xffffffff 3>;59 opp-supported-hw = <0xffffffff 3>;65 opp-supported-hw = <0xffffffff 3>;72 opp-supported-hw = <0xffffffff 2>;80 reg = <0x480025d8 0x24>;82 #size-cells = <0>;87 pinctrl-single,function-mask = <0xff1f>;[all …]
39 #define CEC_VENDOR_ID 0x12fc40 #define CEC_DEV_ID 0x5cec41 #define CEC_SUBID 0x9050228 return 0; in cec_allocate_private()243 board->status = 0; in cec_generic_attach()254 return 0; in cec_generic_attach()273 int isr_flags = 0; in cec_pci_attach()324 return 0; in cec_pci_attach()337 outl(0, cec_priv->plx_iobase + PLX9050_INTCSR_REG); in cec_pci_detach()352 return 0; in cec_pci_probe()[all …]
23 #define SPEED_0 0xffff30 #define MEDIA_TYPE_AUTO_SENSOR 033 #define REG_PM_CTRLSTAT 0x4435 #define REG_PCIE_CAP_LIST 0x5837 #define REG_VPD_CAP 0x6C38 #define VPD_CAP_ID_MASK 0xFF39 #define VPD_CAP_ID_SHIFT 040 #define VPD_CAP_NEXT_PTR_MASK 0xFF42 #define VPD_CAP_VPD_ADDR_MASK 0x7FFF44 #define VPD_CAP_VPD_FLAG 0x80000000[all …]
85 #define OPTION_DISABLED 088 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }100 &num_int_mod_timer, 0);132 return 0; in atl1_validate_option()140 return 0; in atl1_validate_option()143 return 0; in atl1_validate_option()150 return 0; in atl1_validate_option()157 for (i = 0; i < opt->arg.l.nr; i++) { in atl1_validate_option()160 if (ent->str[0] != '\0') in atl1_validate_option()163 return 0; in atl1_validate_option()[all …]
10 #define RCC_SECCFGR0 0x011 #define RCC_SECCFGR1 0x412 #define RCC_SECCFGR2 0x813 #define RCC_SECCFGR3 0xC14 #define RCC_PRIVCFGR0 0x1015 #define RCC_PRIVCFGR1 0x1416 #define RCC_PRIVCFGR2 0x1817 #define RCC_PRIVCFGR3 0x1C18 #define RCC_RCFGLOCKR0 0x2019 #define RCC_RCFGLOCKR1 0x24[all …]
41 #define REG_PM_CTRLSTAT 0x4443 #define REG_PCIE_CAP_LIST 0x5845 #define REG_DEVICE_CAP 0x5C46 #define DEVICE_CAP_MAX_PAYLOAD_MASK 0x747 #define DEVICE_CAP_MAX_PAYLOAD_SHIFT 049 #define REG_DEVICE_CTRL 0x6050 #define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x752 #define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x755 #define REG_VPD_CAP 0x6C56 #define VPD_CAP_ID_MASK 0xff[all …]
11 #define THC_M_PRT_CONTROL_OFFSET 0x100813 #define THC_M_PRT_SPI_CFG_OFFSET 0x101015 #define THC_M_PRT_SPI_ICRRD_OPCODE_OFFSET 0x101417 #define THC_M_PRT_SPI_DMARD_OPCODE_OFFSET 0x101819 #define THC_M_PRT_SPI_WR_OPCODE_OFFSET 0x101C21 #define THC_M_PRT_INT_EN_OFFSET 0x102023 #define THC_M_PRT_INT_STATUS_OFFSET 0x102425 #define THC_M_PRT_ERR_CAUSE_OFFSET 0x102827 #define THC_M_PRT_SW_SEQ_CNTRL_OFFSET 0x104029 #define THC_M_PRT_SW_SEQ_STS_OFFSET 0x1044[all …]
57 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x106258 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x106359 #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */60 #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */61 #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */62 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */63 #define L2CB_V10 0xc064 #define L2CB_V11 0xc165 #define L2CB_V20 0xc066 #define L2CB_V21 0xc1[all …]
16 #define ID_REV (0x00)17 #define ID_REV_ID_MASK_ (0xFFFF0000)18 #define ID_REV_ID_LAN7430_ (0x74300000)19 #define ID_REV_ID_LAN7431_ (0x74310000)20 #define ID_REV_ID_LAN743X_ (0x74300000)21 #define ID_REV_ID_A011_ (0xA0110000) // PCI1101022 #define ID_REV_ID_A041_ (0xA0410000) // PCI1141423 #define ID_REV_ID_A0X1_ (0xA0010000)25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))[all …]
31 // base address: 0x032 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x000033 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x000134 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x000235 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x000336 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x000437 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x000538 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x000639 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x000740 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008[all …]
27 // base address: 0x028 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293430 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293535 // base address: 0x36036 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d43 // base address: 0x6c044 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae446 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae551 // base address: 0xa20[all …]
14 // base address: 0x015 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293417 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293522 // base address: 0x36023 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d30 // base address: 0x6c031 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae433 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae538 // base address: 0xa20[all …]
31 // base address: 0x032 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x293434 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x293539 // base address: 0x36040 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d47 // base address: 0x6c048 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae450 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae555 // base address: 0xa20[all …]
27 // base address: 0x4828 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 035 // base address: 0x3b436 …CRTC8_IDX 0x002d38 …CRTC8_DATA 0x002d40 …GENFC_WT 0x002e42 …GENS1 0x002e[all …]
27 // base address: 0x028 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 032 …VGA_RENDER_CONTROL 0x000034 …VGA_SEQUENCER_RESET_CONTROL 0x000136 …VGA_MODE_CONTROL 0x000238 …VGA_SURFACE_PITCH_SELECT 0x000340 …VGA_MEMORY_BASE_ADDRESS 0x0004[all …]
8 // base address: 0x09 …VGA_MEM_WRITE_PAGE_ADDR 0x000010 …VGA_MEM_WRITE_PAGE_ADDR 0x000011 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 012 …VGA_MEM_READ_PAGE_ADDR 0x000113 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 014 …VGA_RENDER_CONTROL 0x000016 …VGA_SEQUENCER_RESET_CONTROL 0x000118 …VGA_MODE_CONTROL 0x000220 …VGA_SURFACE_PITCH_SELECT 0x0003[all …]
27 // base address: 0x4828 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x001229 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 033 // base address: 0x4c34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x001435 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 039 // base address: 0x040 …DC_PERFMON0_PERFCOUNTER_CNTL 0x002042 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x002144 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022[all …]