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/linux/Documentation/devicetree/bindings/clock/
H A Dmarvell,armada-3700-uart-clock.yaml55 reg = <0x12010 0x4>, <0x12210 0x4>;
56 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>, <&xtalclk>;
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-ipq4019.c112 .reg = 0x2e020,
120 .reg = 0x2f020,
171 return 0; in clk_cpu_div_set_rate()
214 { 384000000, P_XO, 0xd, 0, 0 },
215 { 413000000, P_XO, 0xc, 0, 0 },
216 { 448000000, P_XO, 0xb, 0, 0 },
217 { 488000000, P_XO, 0xa, 0, 0 },
218 { 512000000, P_XO, 0x9, 0, 0 },
219 { 537000000, P_XO, 0x8, 0, 0 },
220 { 565000000, P_XO, 0x7, 0, 0 },
[all …]
H A Dgcc-sc7180.c36 .offset = 0x0,
39 .enable_reg = 0x52010,
40 .enable_mask = BIT(0),
54 { 0x1, 2 },
59 .offset = 0x0,
89 .offset = 0x01000,
92 .enable_reg = 0x52010,
107 .offset = 0x76000,
110 .enable_reg = 0x52010,
125 .offset = 0x13000,
[all …]
H A Dgcc-msm8909.c52 { P_XO, 0 },
64 .offset = 0x21000,
67 .enable_reg = 0x45000,
68 .enable_mask = BIT(0),
80 .offset = 0x21000,
94 .l_reg = 0x20004,
95 .m_reg = 0x20008,
96 .n_reg = 0x2000c,
97 .config_reg = 0x20010,
98 .mode_reg = 0x20000,
[all …]
H A Dgcc-qcs404.c49 { P_XO, 0 },
68 .offset = 0x21000,
71 .enable_reg = 0x45008,
84 .offset = 0x21000,
88 .enable_reg = 0x45000,
89 .enable_mask = BIT(0),
100 .offset = 0x21000,
104 .enable_reg = 0x45000,
105 .enable_mask = BIT(0),
117 .offset = 0x20000,
[all …]
H A Dgcc-msm8917.c54 .offset = 0x21000,
57 .enable_reg = 0x45008,
72 .offset = 0x21000,
75 .enable_reg = 0x45000,
76 .enable_mask = BIT(0),
89 .offset = 0x21000,
102 { 700000000, 1400000000, 0 },
107 .config_ctl_val = 0x4001055b,
108 .early_output_mask = 0,
114 .offset = 0x22000,
[all …]
H A Dgcc-sm7150.c42 .offset = 0x0,
45 .enable_reg = 0x52000,
46 .enable_mask = BIT(0),
59 { 0x0, 1 },
60 { 0x1, 2 },
61 { 0x3, 4 },
62 { 0x7, 8 },
67 .offset = 0x0,
97 .offset = 0x13000,
100 .enable_reg = 0x52000,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8976.c56 .l_reg = 0x21004,
57 .m_reg = 0x21008,
58 .n_reg = 0x2100c,
59 .config_reg = 0x21014,
60 .mode_reg = 0x21000,
61 .status_reg = 0x2101c,
74 .enable_reg = 0x45000,
75 .enable_mask = BIT(0),
89 .l_reg = 0x4a004,
90 .m_reg = 0x4a008,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
H A Dgcc-sc8180x.c43 { 249600000, 2000000000, 0 },
47 .offset = 0x0,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
66 { 0x0, 1 },
67 { 0x1, 2 },
68 { 0x3, 4 },
69 { 0x7, 8 },
74 .offset = 0x0,
89 .offset = 0x1000,
[all …]
H A Dgcc-sc8280xp.c113 .offset = 0x0,
116 .enable_reg = 0x52028,
117 .enable_mask = BIT(0),
128 { 0x1, 2 },
133 .offset = 0x0,
150 .offset = 0x2000,
153 .enable_reg = 0x52028,
165 .offset = 0x76000,
168 .enable_reg = 0x52028,
180 .offset = 0x1a000,
[all …]
H A Dgcc-x1e80100.c52 .offset = 0x0,
55 .enable_reg = 0x52030,
56 .enable_mask = BIT(0),
69 { 0x1, 2 },
74 .offset = 0x0,
91 .offset = 0x4000,
94 .enable_reg = 0x52030,
108 .offset = 0x7000,
111 .enable_reg = 0x52030,
125 .offset = 0x8000,
[all …]
/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_csr.h16 #define MIN_FW_MAJOR_VERSION 0
23 #define PCI_DEVICE_ID_META_FBNIC_ASIC 0x0013
29 #define FBNIC_TWD_L2_HLEN_MASK DESC_GENMASK(5, 0)
33 FBNIC_TWD_L3_TYPE_OTHER = 0,
43 FBNIC_TWD_L4_TYPE_OTHER = 0,
62 FBNIC_TWD_TYPE_META = 0,
71 #define FBNIC_TWD_TS_MASK DESC_GENMASK(39, 0)
72 #define FBNIC_TWD_ADDR_MASK DESC_GENMASK(45, 0)
76 #define FBNIC_TCD_TYPE0_HEAD0_MASK DESC_GENMASK(15, 0)
79 #define FBNIC_TCD_TYPE1_TS_MASK DESC_GENMASK(39, 0)
[all …]
/linux/drivers/infiniband/hw/qib/
H A Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
[all …]