Lines Matching +full:0 +full:x12010
42 .offset = 0x0,
45 .enable_reg = 0x52000,
46 .enable_mask = BIT(0),
59 { 0x0, 1 },
60 { 0x1, 2 },
61 { 0x3, 4 },
62 { 0x7, 8 },
67 .offset = 0x0,
97 .offset = 0x13000,
100 .enable_reg = 0x52000,
114 .offset = 0x27000,
117 .enable_reg = 0x52000,
131 { P_BI_TCXO, 0 },
148 { P_BI_TCXO, 0 },
162 { P_BI_TCXO, 0 },
177 { P_BI_TCXO, 0 },
187 { P_BI_TCXO, 0 },
195 { P_BI_TCXO, 0 },
209 { P_BI_TCXO, 0 },
223 { P_BI_TCXO, 0 },
235 { P_BI_TCXO, 0 },
245 F(19200000, P_BI_TCXO, 1, 0, 0),
250 .cmd_rcgr = 0x48014,
251 .mnd_width = 0,
265 F(19200000, P_BI_TCXO, 1, 0, 0),
270 .cmd_rcgr = 0x4815c,
271 .mnd_width = 0,
284 F(19200000, P_BI_TCXO, 1, 0, 0),
285 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
286 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
287 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
288 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
293 .cmd_rcgr = 0x64004,
307 .cmd_rcgr = 0x65004,
321 .cmd_rcgr = 0x66004,
335 F(9600000, P_BI_TCXO, 2, 0, 0),
336 F(19200000, P_BI_TCXO, 1, 0, 0),
341 .cmd_rcgr = 0x6b028,
355 F(19200000, P_BI_TCXO, 1, 0, 0),
356 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
361 .cmd_rcgr = 0x6f014,
362 .mnd_width = 0,
375 F(19200000, P_BI_TCXO, 1, 0, 0),
376 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
381 .cmd_rcgr = 0x33010,
382 .mnd_width = 0,
397 F(19200000, P_BI_TCXO, 1, 0, 0),
404 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
408 F(120000000, P_GPLL0_OUT_EVEN, 2.5, 0, 0),
421 .cmd_rcgr = 0x17034,
437 .cmd_rcgr = 0x17164,
453 .cmd_rcgr = 0x17294,
469 .cmd_rcgr = 0x173c4,
485 .cmd_rcgr = 0x174f4,
501 .cmd_rcgr = 0x17624,
518 .cmd_rcgr = 0x17754,
535 .cmd_rcgr = 0x17884,
551 .cmd_rcgr = 0x18018,
567 .cmd_rcgr = 0x18148,
583 .cmd_rcgr = 0x18278,
599 .cmd_rcgr = 0x183a8,
615 .cmd_rcgr = 0x184d8,
631 .cmd_rcgr = 0x18608,
647 .cmd_rcgr = 0x18738,
663 .cmd_rcgr = 0x18868,
674 F(19200000, P_BI_TCXO, 1, 0, 0),
677 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
678 F(100000000, P_GPLL0_OUT_EVEN, 3, 0, 0),
679 F(192000000, P_GPLL6_OUT_MAIN, 2, 0, 0),
680 F(384000000, P_GPLL6_OUT_MAIN, 1, 0, 0),
685 .cmd_rcgr = 0x12028,
699 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
700 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
701 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
702 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
707 .cmd_rcgr = 0x12010,
708 .mnd_width = 0,
722 F(9600000, P_BI_TCXO, 2, 0, 0),
723 F(19200000, P_BI_TCXO, 1, 0, 0),
724 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
725 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
726 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
727 F(208000000, P_GPLL7_OUT_MAIN, 4, 0, 0),
732 .cmd_rcgr = 0x1400c,
748 F(9600000, P_BI_TCXO, 2, 0, 0),
749 F(19200000, P_BI_TCXO, 1, 0, 0),
750 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
751 F(33333333, P_GPLL0_OUT_EVEN, 9, 0, 0),
752 F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0),
753 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
758 .cmd_rcgr = 0x1600c,
777 .cmd_rcgr = 0x36010,
791 F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
792 F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
793 F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
794 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
795 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
800 .cmd_rcgr = 0x77020,
814 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
815 F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0),
816 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
817 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
822 .cmd_rcgr = 0x77048,
823 .mnd_width = 0,
836 .cmd_rcgr = 0x77098,
837 .mnd_width = 0,
850 F(37500000, P_GPLL0_OUT_EVEN, 8, 0, 0),
851 F(75000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
852 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
857 .cmd_rcgr = 0x77060,
858 .mnd_width = 0,
871 F(66666667, P_GPLL0_OUT_EVEN, 4.5, 0, 0),
872 F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
873 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
874 F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
879 .cmd_rcgr = 0xf01c,
893 F(19200000, P_BI_TCXO, 1, 0, 0),
894 F(20000000, P_GPLL0_OUT_EVEN, 15, 0, 0),
895 F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0),
896 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
901 .cmd_rcgr = 0xf034,
902 .mnd_width = 0,
915 F(19200000, P_BI_TCXO, 1, 0, 0),
920 .cmd_rcgr = 0xf060,
921 .mnd_width = 0,
934 .cmd_rcgr = 0x7a030,
935 .mnd_width = 0,
948 F(19200000, P_BI_TCXO, 1, 0, 0),
949 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
950 F(600000000, P_GPLL0_OUT_MAIN, 1, 0, 0),
955 .cmd_rcgr = 0x7a018,
956 .mnd_width = 0,
969 .halt_reg = 0x2800c,
972 .enable_reg = 0x2800c,
973 .enable_mask = BIT(0),
982 .halt_reg = 0x82024,
984 .hwcg_reg = 0x82024,
987 .enable_reg = 0x82024,
988 .enable_mask = BIT(0),
1002 .halt_reg = 0x82024,
1004 .hwcg_reg = 0x82024,
1007 .enable_reg = 0x82024,
1022 .halt_reg = 0x8201c,
1025 .enable_reg = 0x8201c,
1026 .enable_mask = BIT(0),
1040 .halt_reg = 0x7a050,
1043 .enable_reg = 0x7a050,
1044 .enable_mask = BIT(0),
1058 .halt_reg = 0x38004,
1060 .hwcg_reg = 0x38004,
1063 .enable_reg = 0x52004,
1073 .halt_reg = 0xb020,
1076 .enable_reg = 0xb020,
1077 .enable_mask = BIT(0),
1086 .halt_reg = 0xb06c,
1089 .enable_reg = 0xb06c,
1090 .enable_mask = BIT(0),
1099 .halt_reg = 0x4100c,
1101 .hwcg_reg = 0x4100c,
1104 .enable_reg = 0x52004,
1114 .halt_reg = 0x41008,
1117 .enable_reg = 0x52004,
1127 .halt_reg = 0x41004,
1130 .enable_reg = 0x52004,
1140 .halt_reg = 0x502c,
1143 .enable_reg = 0x502c,
1144 .enable_mask = BIT(0),
1158 .halt_reg = 0x48000,
1161 .enable_reg = 0x52004,
1176 .halt_reg = 0x48008,
1179 .enable_reg = 0x48008,
1180 .enable_mask = BIT(0),
1194 .halt_reg = 0x4452c,
1197 .enable_reg = 0x4452c,
1198 .enable_mask = BIT(0),
1210 .enable_reg = 0x52004,
1226 .enable_reg = 0x52004,
1240 .halt_reg = 0xb024,
1243 .enable_reg = 0xb024,
1244 .enable_mask = BIT(0),
1253 .halt_reg = 0xb070,
1256 .enable_reg = 0xb070,
1257 .enable_mask = BIT(0),
1267 .halt_reg = 0x64000,
1270 .enable_reg = 0x64000,
1271 .enable_mask = BIT(0),
1285 .halt_reg = 0x65000,
1288 .enable_reg = 0x65000,
1289 .enable_mask = BIT(0),
1303 .halt_reg = 0x66000,
1306 .enable_reg = 0x66000,
1307 .enable_mask = BIT(0),
1323 .enable_reg = 0x52004,
1339 .enable_reg = 0x52004,
1353 .halt_reg = 0x7100c,
1356 .enable_reg = 0x7100c,
1357 .enable_mask = BIT(0),
1366 .halt_reg = 0x71018,
1369 .enable_reg = 0x71018,
1370 .enable_mask = BIT(0),
1379 .halt_reg = 0x7a04c,
1382 .enable_reg = 0x7a04c,
1383 .enable_mask = BIT(0),
1397 .halt_reg = 0x4d008,
1400 .enable_reg = 0x4d008,
1401 .enable_mask = BIT(0),
1410 .halt_reg = 0x4d004,
1412 .hwcg_reg = 0x4d004,
1415 .enable_reg = 0x4d004,
1416 .enable_mask = BIT(0),
1428 .enable_reg = 0x52004,
1444 .enable_reg = 0x52004,
1459 .halt_reg = 0x6b01c,
1462 .enable_reg = 0x5200c,
1477 .halt_reg = 0x6b018,
1479 .hwcg_reg = 0x6b018,
1482 .enable_reg = 0x5200c,
1492 .halt_reg = 0x8c008,
1495 .enable_reg = 0x8c008,
1496 .enable_mask = BIT(0),
1505 .halt_reg = 0x6b014,
1508 .enable_reg = 0x5200c,
1518 .halt_reg = 0x6b020,
1521 .enable_reg = 0x5200c,
1531 .halt_reg = 0x6b010,
1533 .hwcg_reg = 0x6b010,
1536 .enable_reg = 0x5200c,
1537 .enable_mask = BIT(0),
1546 .halt_reg = 0x6b00c,
1549 .enable_reg = 0x5200c,
1559 .halt_reg = 0x6f004,
1562 .enable_reg = 0x6f004,
1563 .enable_mask = BIT(0),
1577 .halt_reg = 0x6f02c,
1580 .enable_reg = 0x6f02c,
1581 .enable_mask = BIT(0),
1595 .halt_reg = 0x3300c,
1598 .enable_reg = 0x3300c,
1599 .enable_mask = BIT(0),
1613 .halt_reg = 0x33004,
1615 .hwcg_reg = 0x33004,
1618 .enable_reg = 0x33004,
1619 .enable_mask = BIT(0),
1628 .halt_reg = 0x33008,
1631 .enable_reg = 0x33008,
1632 .enable_mask = BIT(0),
1641 .halt_reg = 0x34004,
1643 .hwcg_reg = 0x34004,
1646 .enable_reg = 0x52004,
1656 .halt_reg = 0x17014,
1659 .enable_reg = 0x5200c,
1669 .halt_reg = 0x1700c,
1672 .enable_reg = 0x5200c,
1682 .halt_reg = 0x17030,
1685 .enable_reg = 0x5200c,
1700 .halt_reg = 0x17160,
1703 .enable_reg = 0x5200c,
1718 .halt_reg = 0x17290,
1721 .enable_reg = 0x5200c,
1736 .halt_reg = 0x173c0,
1739 .enable_reg = 0x5200c,
1754 .halt_reg = 0x174f0,
1757 .enable_reg = 0x5200c,
1772 .halt_reg = 0x17620,
1775 .enable_reg = 0x5200c,
1790 .halt_reg = 0x17750,
1793 .enable_reg = 0x5200c,
1808 .halt_reg = 0x17880,
1811 .enable_reg = 0x5200c,
1826 .halt_reg = 0x18004,
1829 .enable_reg = 0x5200c,
1839 .halt_reg = 0x18008,
1842 .enable_reg = 0x5200c,
1852 .halt_reg = 0x18014,
1855 .enable_reg = 0x5200c,
1870 .halt_reg = 0x18144,
1873 .enable_reg = 0x5200c,
1888 .halt_reg = 0x18274,
1891 .enable_reg = 0x5200c,
1906 .halt_reg = 0x183a4,
1909 .enable_reg = 0x5200c,
1924 .halt_reg = 0x184d4,
1927 .enable_reg = 0x5200c,
1942 .halt_reg = 0x18604,
1945 .enable_reg = 0x5200c,
1960 .halt_reg = 0x18734,
1963 .enable_reg = 0x5200c,
1978 .halt_reg = 0x18864,
1981 .enable_reg = 0x5200c,
1996 .halt_reg = 0x17004,
1999 .enable_reg = 0x5200c,
2009 .halt_reg = 0x17008,
2011 .hwcg_reg = 0x17008,
2014 .enable_reg = 0x5200c,
2024 .halt_reg = 0x1800c,
2027 .enable_reg = 0x5200c,
2037 .halt_reg = 0x18010,
2039 .hwcg_reg = 0x18010,
2042 .enable_reg = 0x5200c,
2052 .halt_reg = 0x12008,
2055 .enable_reg = 0x12008,
2056 .enable_mask = BIT(0),
2065 .halt_reg = 0x1200c,
2068 .enable_reg = 0x1200c,
2069 .enable_mask = BIT(0),
2083 .halt_reg = 0x12040,
2086 .enable_reg = 0x12040,
2087 .enable_mask = BIT(0),
2101 .halt_reg = 0x14008,
2104 .enable_reg = 0x14008,
2105 .enable_mask = BIT(0),
2114 .halt_reg = 0x14004,
2117 .enable_reg = 0x14004,
2118 .enable_mask = BIT(0),
2132 .halt_reg = 0x16008,
2135 .enable_reg = 0x16008,
2136 .enable_mask = BIT(0),
2145 .halt_reg = 0x16004,
2148 .enable_reg = 0x16004,
2149 .enable_mask = BIT(0),
2163 .halt_reg = 0x4144,
2166 .enable_reg = 0x52004,
2167 .enable_mask = BIT(0),
2181 .halt_reg = 0x36004,
2184 .enable_reg = 0x36004,
2185 .enable_mask = BIT(0),
2194 .halt_reg = 0x3600c,
2197 .enable_reg = 0x3600c,
2198 .enable_mask = BIT(0),
2207 .halt_reg = 0x36008,
2210 .enable_reg = 0x36008,
2211 .enable_mask = BIT(0),
2225 .halt_reg = 0x8c000,
2228 .enable_reg = 0x8c000,
2229 .enable_mask = BIT(0),
2238 .halt_reg = 0x77014,
2240 .hwcg_reg = 0x77014,
2243 .enable_reg = 0x77014,
2244 .enable_mask = BIT(0),
2253 .halt_reg = 0x77038,
2255 .hwcg_reg = 0x77038,
2258 .enable_reg = 0x77038,
2259 .enable_mask = BIT(0),
2273 .halt_reg = 0x77038,
2275 .hwcg_reg = 0x77038,
2278 .enable_reg = 0x77038,
2293 .halt_reg = 0x77090,
2295 .hwcg_reg = 0x77090,
2298 .enable_reg = 0x77090,
2299 .enable_mask = BIT(0),
2313 .halt_reg = 0x77090,
2315 .hwcg_reg = 0x77090,
2318 .enable_reg = 0x77090,
2333 .halt_reg = 0x77094,
2335 .hwcg_reg = 0x77094,
2338 .enable_reg = 0x77094,
2339 .enable_mask = BIT(0),
2353 .halt_reg = 0x77094,
2355 .hwcg_reg = 0x77094,
2358 .enable_reg = 0x77094,
2373 .halt_reg = 0x7701c,
2376 .enable_reg = 0x7701c,
2377 .enable_mask = BIT(0),
2386 .halt_reg = 0x77018,
2389 .enable_reg = 0x77018,
2390 .enable_mask = BIT(0),
2399 .halt_reg = 0x7708c,
2401 .hwcg_reg = 0x7708c,
2404 .enable_reg = 0x7708c,
2405 .enable_mask = BIT(0),
2419 .halt_reg = 0x7708c,
2421 .hwcg_reg = 0x7708c,
2424 .enable_reg = 0x7708c,
2439 .halt_reg = 0xf010,
2442 .enable_reg = 0xf010,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0xf018,
2460 .enable_reg = 0xf018,
2461 .enable_mask = BIT(0),
2475 .halt_reg = 0xf014,
2478 .enable_reg = 0xf014,
2479 .enable_mask = BIT(0),
2488 .halt_reg = 0x8c010,
2491 .enable_reg = 0x8c010,
2492 .enable_mask = BIT(0),
2501 .halt_reg = 0xf050,
2504 .enable_reg = 0xf050,
2505 .enable_mask = BIT(0),
2519 .halt_reg = 0xf054,
2522 .enable_reg = 0xf054,
2523 .enable_mask = BIT(0),
2539 .enable_reg = 0xf058,
2540 .enable_mask = BIT(0),
2549 .halt_reg = 0x6a004,
2551 .hwcg_reg = 0x6a004,
2554 .enable_reg = 0x6a004,
2555 .enable_mask = BIT(0),
2564 .halt_reg = 0x7a00c,
2567 .enable_reg = 0x7a00c,
2568 .enable_mask = BIT(0),
2582 .halt_reg = 0x7a004,
2585 .enable_reg = 0x7a004,
2586 .enable_mask = BIT(0),
2600 .halt_reg = 0x7a008,
2603 .enable_reg = 0x7a008,
2604 .enable_mask = BIT(0),
2619 .halt_reg = 0xb01c,
2622 .enable_reg = 0xb01c,
2623 .enable_mask = BIT(0),
2632 .halt_reg = 0x7a014,
2634 .hwcg_reg = 0x7a014,
2637 .enable_reg = 0x7a014,
2638 .enable_mask = BIT(0),
2647 .halt_reg = 0x7a010,
2650 .enable_reg = 0x7a010,
2651 .enable_mask = BIT(0),
2665 .gdscr = 0x6b004,
2673 .gdscr = 0x77004,
2681 .gdscr = 0xf004,
2689 .gdscr = 0x7d030,
2698 .gdscr = 0x7d03c,
2707 .gdscr = 0x7d034,
2716 .gdscr = 0x7d038,
2725 .gdscr = 0x7d040,
2734 .gdscr = 0x7d048,
2743 .gdscr = 0x7d044,
2911 [GCC_PCIE_0_BCR] = { 0x6b000 },
2912 [GCC_PCIE_PHY_BCR] = { 0x6f000 },
2913 [GCC_PCIE_PHY_COM_BCR] = { 0x6f010 },
2914 [GCC_UFS_PHY_BCR] = { 0x77000 },
2915 [GCC_USB30_PRIM_BCR] = { 0xf000 },
2916 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
2917 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
2918 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
2919 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
2920 [GCC_QUSB2PHY_PRIM_BCR] = { 0x26000 },
2921 [GCC_VIDEO_AXI_CLK_BCR] = { .reg = 0xb01c, .bit = 2, .udelay = 150 },
2966 .max_register = 0x1820b0,
3001 regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3); in gcc_sm7150_probe()
3002 regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); in gcc_sm7150_probe()
3003 regmap_update_bits(regmap, 0x71028, 0x3, 0x3); in gcc_sm7150_probe()
3006 qcom_branch_set_clk_en(regmap, 0x48004); /* GCC_CPUSS_GNOC_CLK */ in gcc_sm7150_probe()
3007 qcom_branch_set_clk_en(regmap, 0x0b004); /* GCC_VIDEO_AHB_CLK */ in gcc_sm7150_probe()
3008 qcom_branch_set_clk_en(regmap, 0x0b008); /* GCC_CAMERA_AHB_CLK */ in gcc_sm7150_probe()
3009 qcom_branch_set_clk_en(regmap, 0x0b00c); /* GCC_DISP_AHB_CLK */ in gcc_sm7150_probe()
3010 qcom_branch_set_clk_en(regmap, 0x0b02c); /* GCC_CAMERA_XO_CLK */ in gcc_sm7150_probe()
3011 qcom_branch_set_clk_en(regmap, 0x0b028); /* GCC_VIDEO_XO_CLK */ in gcc_sm7150_probe()
3012 qcom_branch_set_clk_en(regmap, 0x0b030); /* GCC_DISP_XO_CLK */ in gcc_sm7150_probe()
3013 qcom_branch_set_clk_en(regmap, 0x71004); /* GCC_GPU_CFG_AHB_CLK */ in gcc_sm7150_probe()