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Searched +full:0 +full:x11c10000 (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,mt8365-csi-rx.yaml32 enum: [0, 1]
34 If the PHY doesn't support mode selection then #phy-cells must be 0 and
66 reg = <0 0x11c10000 0 0x2000>;
73 reg = <0 0x11c12000 0 0x2000>;
76 #phy-cells = <0>;
/linux/Documentation/devicetree/bindings/nvmem/
H A Dmediatek,efuse.yaml23 pattern: "^efuse@[0-9a-f]+$"
71 reg = <0x11c10000 0x1000>;
76 reg = <0x184 0x1>;
77 bits = <0 5>;
80 reg = <0x184 0x2>;
84 reg = <0x185 0x1>;
88 reg = <0x186 0x1>;
89 bits = <0 5>;
92 reg = <0x186 0x2>;
96 reg = <0x187 0x1>;
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt7981-pinctrl.yaml85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
396 enum: [0, 1, 2, 3]
400 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/linux/drivers/clk/samsung/
H A Dclk-fsd.c23 /* Register Offset definitions for CMU_CMU (0x11c10000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0
25 #define PLL_LOCKTIME_PLL_SHARED1 0x4
26 #define PLL_LOCKTIME_PLL_SHARED2 0x8
27 #define PLL_LOCKTIME_PLL_SHARED3 0xc
28 #define PLL_CON0_PLL_SHARED0 0x100
29 #define PLL_CON0_PLL_SHARED1 0x120
30 #define PLL_CON0_PLL_SHARED2 0x140
31 #define PLL_CON0_PLL_SHARED3 0x160
32 #define MUX_CMU_CIS0_CLKMUX 0x1000
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]