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/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-bk4.dts20 reg = <0x80000000 0x8000000>;
25 #clock-cells = <0>;
31 #clock-cells = <0>;
38 pinctrl-0 = <&pinctrl_gpio_leds>;
66 pinctrl-0 = <&pinctrl_gpio_spi>;
69 #size-cells = <0>;
74 num-chipselects = <0>;
76 gpio@0 {
78 reg = <0>;
100 pinctrl-0 = <&pinctrl_can0>;
[all …]
H A Dvf610-zii-ssmb-dtu.dts28 reg = <0x80000000 0x20000000>;
33 pinctrl-0 = <&pinctrl_leds_debug>;
79 pinctrl-0 = <&pinctrl_esdhc0>;
91 pinctrl-0 = <&pinctrl_esdhc1>;
100 pinctrl-0 = <&pinctrl_fec1>;
110 #size-cells = <0>;
115 switch0: ethernet-switch@0 {
117 pinctrl-0 = <&pinctrl_gpio_switch0>;
119 reg = <0>;
128 #size-cells = <0>;
[all …]
H A Dvf610-zii-scu4-aib.dts18 reg = <0x80000000 0x20000000>;
23 pinctrl-0 = <&pinctrl_leds_debug>;
28 gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
35 pinctrl-0 = <&pinctrl_mdio_mux>;
43 #size-cells = <0>;
48 #size-cells = <0>;
50 switch0: ethernet-switch@0 {
52 reg = <0>;
53 dsa,member = <0 0>;
58 #size-cells = <0>;
[all …]
H A Dvf610-twr.dts18 reg = <0x80000000 0x8000000>;
23 #clock-cells = <0>;
29 #clock-cells = <0>;
80 pinctrl-0 = <&pinctrl_adc0_ad5>;
95 bus-num = <0>;
97 pinctrl-0 = <&pinctrl_dspi0>;
100 sflash: at26df081a@0 {
107 reg = <0>;
117 pinctrl-0 = <&pinctrl_esdhc1>;
127 pinctrl-0 = <&pinctrl_fec0>;
[all …]
H A Dvf610-zii-spb4.dts24 reg = <0x80000000 0x20000000>;
29 pinctrl-0 = <&pinctrl_leds_debug>;
68 pinctrl-0 = <&pinctrl_dspi1>;
71 flash@0 {
75 reg = <0>;
90 pinctrl-0 = <&pinctrl_esdhc0>;
102 pinctrl-0 = <&pinctrl_esdhc1>;
111 pinctrl-0 = <&pinctrl_fec1>;
121 #size-cells = <0>;
126 switch0: ethernet-switch@0 {
[all …]
H A Dvf610-zii-ssmb-spu3.dts28 reg = <0x80000000 0x20000000>;
33 pinctrl-0 = <&pinctrl_leds_debug>;
72 pinctrl-0 = <&pinctrl_dspi1>;
80 flash@0 {
84 reg = <0>;
87 partition@0 {
88 label = "m25p128-0";
89 reg = <0x0 0x01000000>;
104 pinctrl-0 = <&pinctrl_esdhc0>;
116 pinctrl-0 = <&pinctrl_esdhc1>;
[all …]
H A Dvf610-zii-cfu1.dts20 reg = <0x80000000 0x20000000>;
25 pinctrl-0 = <&pinctrl_leds_debug>;
68 pinctrl-0 = <&pinctrl_optical>;
97 pinctrl-0 = <&pinctrl_dspi1>;
105 flash@0 {
109 reg = <0>;
112 partition@0 {
113 label = "m25p128-0";
114 reg = <0x0 0x01000000>;
129 pinctrl-0 = <&pinctrl_esdhc0>;
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux/include/media/
H A Ddvb-usb-ids.h23 #define USB_VID_774 0x7a69
24 #define USB_VID_ADSTECH 0x06e1
25 #define USB_VID_AFATECH 0x15a4
26 #define USB_VID_ALCOR_MICRO 0x058f
27 #define USB_VID_ALINK 0x05e3
28 #define USB_VID_AME 0x06be
29 #define USB_VID_AMT 0x1c73
30 #define USB_VID_ANCHOR 0x0547
31 #define USB_VID_ANSONIC 0x10b9
32 #define USB_VID_ANUBIS_ELECTRONIC 0x10fd
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/linux/drivers/net/usb/
H A Dcdc_ether.c28 desc->bInterfaceProtocol == 0xff); in is_rndis()
54 #define is_rndis(desc) 0
55 #define is_activesync(desc) 0
56 #define is_wireless_rndis(desc) 0
57 #define is_novatel_rndis(desc) 0
62 0xa3, 0x17, 0xa8, 0x8b, 0x04, 0x5e, 0x4f, 0x01,
63 0xa6, 0x07, 0xc0, 0xff, 0xcb, 0x7e, 0x39, 0x2a,
83 usb_sndctrlpipe(dev->udev, 0), in usbnet_cdc_update_filter()
89 0, in usbnet_cdc_update_filter()
130 if (len == 0 && dev->udev->actconfig->extralen) { in usbnet_generic_cdc_bind()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/drivers/media/usb/gspca/
H A Dsn9c20x.c26 #define SCALE_MASK 0x0f
27 #define SCALE_160x120 0
31 #define MODE_RAW 0x10
32 #define MODE_JPEG 0x20
33 #define MODE_SXGA 0x80
35 #define SENSOR_OV9650 0
50 #define HAS_NO_BUTTON 0x1
51 #define LED_REVERSE 0x2 /* some cameras unset gpio to turn on leds */
52 #define FLIP_DETECT 0x4
53 #define HAS_LED_TORCH 0x8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
/linux/sound/soc/codecs/
H A Dwm8962.h16 #define WM8962_SYSCLK_MCLK 0
30 #define WM8962_LEFT_INPUT_VOLUME 0x00
31 #define WM8962_RIGHT_INPUT_VOLUME 0x01
32 #define WM8962_HPOUTL_VOLUME 0x02
33 #define WM8962_HPOUTR_VOLUME 0x03
34 #define WM8962_CLOCKING1 0x04
35 #define WM8962_ADC_DAC_CONTROL_1 0x05
36 #define WM8962_ADC_DAC_CONTROL_2 0x06
37 #define WM8962_AUDIO_INTERFACE_0 0x07
38 #define WM8962_CLOCKING2 0x08
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h29 // base address: 0x0
30 …DIDT_SQ_CTRL0 0x0000
31 …DIDT_SQ_CTRL2 0x0002
32 …DIDT_SQ_STALL_CTRL 0x0004
33 …DIDT_SQ_TUNING_CTRL 0x0005
34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006
35 …DIDT_SQ_CTRL3 0x0007
36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008
37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009
38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a
[all …]
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_2_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
H A Dgc_9_4_3_offset.h29 // base address: 0x8000
30 …GRBM_CNTL 0x0000
31 …e regGRBM_CNTL_BASE_IDX 0
32 …GRBM_SKEW_CNTL 0x0001
33 …e regGRBM_SKEW_CNTL_BASE_IDX 0
34 …GRBM_STATUS2 0x0002
35 …e regGRBM_STATUS2_BASE_IDX 0
36 …GRBM_PWR_CNTL 0x0003
37 …e regGRBM_PWR_CNTL_BASE_IDX 0
38 …GRBM_STATUS 0x0004
[all …]
H A Dgc_9_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_mbx.c33 for (i = 0; i < ARRAY_SIZE(mb_str); i++) { in mb_to_str()
77 for (i = 0; i < ARRAY_SIZE(rom_cmds); i++) { in is_rom_cmd()
83 return 0; in is_rom_cmd()
98 * 0 : QLA_SUCCESS = cmd performed success
109 unsigned long flags = 0; in qla2x00_mailbox_command()
113 uint16_t command = 0; in qla2x00_mailbox_command()
124 ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__); in qla2x00_mailbox_command()
127 ql_log(ql_log_warn, vha, 0x1001, in qla2x00_mailbox_command()
133 ql_log(ql_log_warn, vha, 0x1002, in qla2x00_mailbox_command()
141 ql_log(ql_log_warn, vha, 0xd04e, in qla2x00_mailbox_command()
[all …]

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