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/linux/include/linux/
H A Dkernelcapi.h19 #define CAPI_NOERROR 0x0000
21 #define CAPI_TOOMANYAPPLS 0x1001
22 #define CAPI_LOGBLKSIZETOSMALL 0x1002
23 #define CAPI_BUFFEXECEEDS64K 0x1003
24 #define CAPI_MSGBUFSIZETOOSMALL 0x1004
25 #define CAPI_ANZLOGCONNNOTSUPPORTED 0x1005
26 #define CAPI_REGRESERVED 0x1006
27 #define CAPI_REGBUSY 0x1007
28 #define CAPI_REGOSRESOURCEERR 0x1008
29 #define CAPI_REGNOTINSTALLED 0x1009
[all …]
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux/drivers/mfd/
H A Dwm8994-regmap.c18 { 0x0001, 0x0000 }, /* R1 - Power Management (1) */
19 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
20 { 0x0003, 0x0000 }, /* R3 - Power Management (3) */
21 { 0x0004, 0x0000 }, /* R4 - Power Management (4) */
22 { 0x0005, 0x0000 }, /* R5 - Power Management (5) */
23 { 0x0006, 0x0000 }, /* R6 - Power Management (6) */
24 { 0x0015, 0x0000 }, /* R21 - Input Mixer (1) */
25 { 0x0018, 0x008B }, /* R24 - Left Line Input 1&2 Volume */
26 { 0x0019, 0x008B }, /* R25 - Left Line Input 3&4 Volume */
27 { 0x001A, 0x008B }, /* R26 - Right Line Input 1&2 Volume */
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.h10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0)
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
28 #define HCLGE_COMM_TYPE_CRQ 0
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/linux/drivers/net/wireless/ath/ath11k/
H A Dpci.c22 #define ATH11K_PCI_BAR_NUM 0
26 #define TCSR_SOC_HW_VERSION 0x0224
28 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
30 #define QCA6390_DEVICE_ID 0x1101
31 #define QCN9074_DEVICE_ID 0x1104
32 #define WCN6855_DEVICE_ID 0x1103
34 #define TCSR_SOC_HW_SUB_VER 0x1910010
159 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
160 { .name = "CE", .num_vectors = 1, .base_vector = 0 },
161 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
[all …]
/linux/sound/soc/codecs/
H A Dwm8996.c110 return 0; \
113 WM8996_REGULATOR_EVENT(0)
118 { WM8996_POWER_MANAGEMENT_1, 0x0 },
119 { WM8996_POWER_MANAGEMENT_2, 0x0 },
120 { WM8996_POWER_MANAGEMENT_3, 0x0 },
121 { WM8996_POWER_MANAGEMENT_4, 0x0 },
122 { WM8996_POWER_MANAGEMENT_5, 0x0 },
123 { WM8996_POWER_MANAGEMENT_6, 0x0 },
124 { WM8996_POWER_MANAGEMENT_7, 0x10 },
125 { WM8996_POWER_MANAGEMENT_8, 0x
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H A Drt5682s.h21 #define RT5682S_RESET 0x0000
22 #define RT5682S_VERSION_ID 0x00fd
23 #define RT5682S_VENDOR_ID 0x00fe
24 #define RT5682S_DEVICE_ID 0x00ff
26 #define RT5682S_HP_CTRL_1 0x0002
27 #define RT5682S_HP_CTRL_2 0x0003
28 #define RT5682S_HPL_GAIN 0x0005
29 #define RT5682S_HPR_GAIN 0x0006
31 #define RT5682S_I2C_CTRL 0x0008
34 #define RT5682S_CBJ_BST_CTRL 0x000b
[all …]
H A Dwm8962.c101 return 0; \
104 WM8962_REGULATOR_EVENT(0)
114 { 0, 0x009F }, /* R0 - Left Input volume */
115 { 1, 0x049F }, /* R1 - Right Input volume */
116 { 2, 0x0000 }, /* R2 - HPOUTL volume */
117 { 3, 0x0000 }, /* R3 - HPOUTR volume */
119 { 5, 0x0018 }, /* R5 - ADC & DAC Control 1 */
120 { 6, 0x2008 }, /* R6 - ADC & DAC Control 2 */
121 { 7, 0x000A }, /* R7 - Audio Interface 0 */
122 { 8, 0x01E4 }, /* R8 - Clocking2 */
[all …]
H A Dwm5100-tables.c815 { 0x0000, 0x0000 }, /* R0 - software reset */
816 { 0x0001, 0x0000 }, /* R1 - Device Revision */
817 { 0x0010, 0x0801 }, /* R16 - Ctrl IF 1 */
818 { 0x0020, 0x0000 }, /* R32 - Tone Generator 1 */
819 { 0x0030, 0x0000 }, /* R48 - PWM Drive 1 */
820 { 0x0031, 0x0100 }, /* R49 - PWM Drive 2 */
821 { 0x0032, 0x0100 }, /* R50 - PWM Drive 3 */
822 { 0x0100, 0x0002 }, /* R256 - Clocking 1 */
823 { 0x0101, 0x0000 }, /* R257 - Clocking 3 */
824 { 0x0102, 0x0011 }, /* R258 - Clocking 4 */
[all …]
H A Drt5682s.c32 #define DEVICE_ID 0x6749
50 {RT5682S_I2C_CTRL, 0x0007},
51 {RT5682S_DIG_IN_CTRL_1, 0x0000},
52 {RT5682S_CHOP_DAC_2, 0x2020},
53 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_2, 0x0101},
54 {RT5682S_VREF_REC_OP_FB_CAP_CTRL_1, 0x80c0},
55 {RT5682S_HP_CALIB_CTRL_9, 0x0002},
56 {RT5682S_DEPOP_1, 0x0000},
57 {RT5682S_HP_CHARGE_PUMP_2, 0x3c15},
58 {RT5682S_DAC1_DIG_VOL, 0xfefe},
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/accel/ivpu/
H A Dvpu_jsm_api.h30 #define VPU_JSM_API_VER_PATCH 0
39 * Bands: Idle(0), Normal(1), Focus(2), RealTime(3)
55 #define VPU_ENGINE_COMPUTE 0
61 #define VPU_JSM_STATUS_SUCCESS 0x0U
62 #define VPU_JSM_STATUS_PARSING_ERR 0x1U
63 #define VPU_JSM_STATUS_PROCESSING_ERR 0x2U
64 #define VPU_JSM_STATUS_PREEMPTED 0x3U
65 #define VPU_JSM_STATUS_ABORTED 0x4U
66 #define VPU_JSM_STATUS_USER_CTX_VIOL_ERR 0x5U
67 #define VPU_JSM_STATUS_GLOBAL_CTX_VIOL_ERR 0x6U
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/net/ethernet/marvell/prestera/
H A Dprestera_hw.c22 PRESTERA_CMD_TYPE_SWITCH_INIT = 0x1,
23 PRESTERA_CMD_TYPE_SWITCH_ATTR_SET = 0x2,
25 PRESTERA_CMD_TYPE_PORT_ATTR_SET = 0x100,
26 PRESTERA_CMD_TYPE_PORT_ATTR_GET = 0x101,
27 PRESTERA_CMD_TYPE_PORT_INFO_GET = 0x110,
29 PRESTERA_CMD_TYPE_VLAN_CREATE = 0x200,
30 PRESTERA_CMD_TYPE_VLAN_DELETE = 0x201,
31 PRESTERA_CMD_TYPE_VLAN_PORT_SET = 0x202,
32 PRESTERA_CMD_TYPE_VLAN_PVID_SET = 0x203,
34 PRESTERA_CMD_TYPE_FDB_ADD = 0x300,
[all …]
/linux/drivers/net/ethernet/8390/
H A Dpcnet_cs.c53 #define PCNET_CMD 0x00
54 #define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
55 #define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
56 #define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */
58 #define PCNET_START_PG 0x40 /* First page of TX buffer */
59 #define PCNET_STOP_PG 0x80 /* Last page +1 of RX ring */
62 #define SOCKET_START_PG 0x01
63 #define SOCKET_STOP_PG 0xff
77 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
81 INT_MODULE_PARM(mem_speed, 0); /* shared mem speed, in ns */
[all …]
/linux/drivers/input/joystick/
H A Dxpad.c80 #define MAP_DPAD_TO_BUTTONS BIT(0)
91 #define XTYPE_XBOX 0
102 #define PKT_XB 0
108 #define FLAG_DELAY_INIT BIT(0)
135 { 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 },
136 { 0x03eb, 0xff01, "Wooting One (Legacy)", 0, XTYPE_XBOX360 },
137 { 0x03eb, 0xff02, "Wooting Two (Legacy)", 0, XTYPE_XBOX360 },
138 { 0x03f0, 0x038D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wired */
139 { 0x03f0, 0x048D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wireless */
140 { 0x03f0, 0x0495, "HyperX Clutch Gladiate", 0, XTYPE_XBOXONE },
[all …]
/linux/drivers/net/wireless/ath/wil6210/
H A Dwmi.h27 #define WMI_INVALID_TEMPERATURE (0xFFFFFFFF)
55 #define WMI_QOS_SET_VIF_PRIORITY (0xFF)
63 MID_DEFAULT = 0x00,
64 FIRST_DBG_MID_ID = 0x10,
65 LAST_DBG_MID_ID = 0xFE,
66 MID_BROADCAST = 0xFF,
74 WMI_FW_CAPABILITY_FTM = 0,
115 WMI_CONNECT_CMDID = 0x01,
116 WMI_DISCONNECT_CMDID = 0x03,
117 WMI_DISCONNECT_STA_CMDID = 0x04,
[all …]
/linux/sound/pci/ac97/
H A Dac97_patch.c32 for (idx = 0; idx < count; idx++) { in patch_build_controls()
34 if (err < 0) in patch_build_controls()
37 return 0; in patch_build_controls()
79 ucontrol->value.enumerated.item[0] = ac97->indep_surround; in ac97_surround_jack_mode_get()
80 return 0; in ac97_surround_jack_mode_get()
86 unsigned char indep = !!ucontrol->value.enumerated.item[0]; in ac97_surround_jack_mode_put()
94 return 0; in ac97_surround_jack_mode_put()
108 ucontrol->value.enumerated.item[0] = ac97->channel_mode; in ac97_channel_mode_get()
109 return 0; in ac97_channel_mode_get()
115 unsigned char mode = ucontrol->value.enumerated.item[0]; in ac97_channel_mode_put()
[all...]

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