/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6ull-jozacp.dts | 25 led-0 { 28 function-enumerator = <0>; 29 pwms = <&pwm1 0 10000000 0>; 37 pwms = <&pwm3 0 10000000 0>; 45 pwms = <&pwm5 0 10000000 0>; 59 pwms = <&pwm2 0 10000000 0>; 67 pwms = <&pwm4 0 10000000 0>; 75 pwms = <&pwm6 0 10000000 0>; 98 pinctrl-0 = <&pinctrl_vbus>; 110 pinctrl-0 = <&pinctrl_wifi_npd>; [all …]
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/linux/Documentation/devicetree/bindings/i2c/ |
H A D | marvell,mv64xxx-i2c.yaml | 119 reg = <0x11000 0x20>; 127 reg = <0x11000 0x100>; 135 reg = <0x701000 0x20>;
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/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
H A D | srio.txt | 9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0. 20 be set to 0x11000. 83 reg = <0xf 0xfe0c0000 0 0x11000>; 94 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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H A D | mpc5121-psc.txt | 55 cell-index = <0>; 56 reg = <0x11000 0x100>; 57 interrupts = <40 0x8>; 66 reg = <0x11100 0x100>; 67 interrupts = <40 0x8>; 75 reg = <0x11f00 0x100>; 76 interrupts = <40 0x8>;
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/linux/drivers/of/unittest-data/ |
H A D | tests-address.dtsi | 17 ranges = <0x70000000 0x70000000 0x50000000>, 18 <0x00000000 0xd0000000 0x20000000>; 19 dma-ranges = <0x0 0x20000000 0x40000000>; 22 reg = <0x70000000 0x1000>; 28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>; 29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>; 32 reg = <0x0 0x1000 0x0 0x1000>; 40 reg = <0x90000000 0x1000>; 41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>; 42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>, [all …]
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/linux/drivers/media/pci/cx25821/ |
H A D | cx25821-sram.h | 12 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */ 17 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */ 27 /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */ 29 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */ 37 /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */ 40 #define RX_SRAM_START 0x10000 41 #define VID_A_DOWN_CMDS 0x10000 42 #define VID_B_DOWN_CMDS 0x10050 43 #define VID_C_DOWN_CMDS 0x100A0 44 #define VID_D_DOWN_CMDS 0x100F0 [all …]
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/linux/sound/sh/ |
H A D | aica.h | 11 #define G2_FIFO 0xa05f688c 12 #define SPU_MEMORY_BASE 0xA0800000 13 #define ARM_RESET_REGISTER 0xA0702C00 14 #define SPU_REGISTER_BASE 0xA0700000 17 #define AICA_CONTROL_POINT 0xA0810000 18 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008 19 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004 22 #define AICA_CMD_KICK 0x80000000 23 #define AICA_CMD_NONE 0 30 #define SM_16BIT 0 [all …]
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/linux/Documentation/devicetree/bindings/mtd/ |
H A D | lpc32xx-mlc.txt | 28 reg = <0x200A8000 0x11000>; 29 interrupts = <11 0>; 44 reg = <0x00000000 0x00064000>;
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/linux/arch/m68k/include/asm/ |
H A D | apollohw.h | 52 #define IO_BASE 0x80000000 62 #define SAU7_SIO01_PHYSADDR 0x10400 63 #define SAU7_SIO23_PHYSADDR 0x10500 64 #define SAU7_RTC_PHYSADDR 0x10900 65 #define SAU7_PICA 0x11000 66 #define SAU7_PICB 0x11100 67 #define SAU7_CPUCTRL 0x10100 68 #define SAU7_TIMER 0x010800 70 #define SAU8_SIO01_PHYSADDR 0x8400 71 #define SAU8_RTC_PHYSADDR 0x8900 [all …]
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/linux/Documentation/devicetree/bindings/clock/ti/davinci/ |
H A D | pll.txt | 30 - #clock-cells: shall be 0 45 - #clock-cells: shall be 0 51 - #clock-cells: shall be 0 58 reg = <0x11000 0x1000>; 64 #clock-cells = <0>; 72 #clock-cells = <0>; 76 #clock-cells = <0>; 82 reg = <0x21a000 0x1000>; 91 #clock-cells = <0>;
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/linux/arch/powerpc/platforms/embedded6xx/ |
H A D | storcenter.c | 34 return 0; in storcenter_device_probe() 53 hose->first_busno = bus_range ? bus_range[0] : 0; in storcenter_add_bridge() 54 hose->last_busno = bus_range ? bus_range[1] : 0xff; in storcenter_add_bridge() 56 setup_indirect_pci(hose, MPC10X_MAPB_CNFG_ADDR, MPC10X_MAPB_CNFG_DATA, 0); in storcenter_add_bridge() 63 return 0; in storcenter_add_bridge() 88 mpic = mpic_alloc(NULL, 0, 0, 16, 0, " OpenPIC "); in storcenter_init_IRQ() 93 * I2C is the second internal, so it is at 17, 0x11020. in storcenter_init_IRQ() 95 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200); in storcenter_init_IRQ() 96 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000); in storcenter_init_IRQ()
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | b4860qds.dts | 50 board-control@3,0 { 79 reg = <0x1e>; 84 reg = <0x1f>; 92 reg = <0x7>; 98 reg = <0x6>; 106 reg = <0xf 0xfe0c0000 0 0x11000>; 109 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 112 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
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H A D | ppa8548.dts | 22 reg = <0 0 0x0 0x40000000>; 26 reg = <0xf 0xe0005000 0 0x1000>; 27 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>; 31 ranges = <0 0xf 0xe0000000 0x100000>; 50 reg = <0xf 0xe00c0000 0x0 0x11000>; 52 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>; 58 nor@0 { 62 reg = <0x0 0x0 0x00800000>; 66 partition@0 { 67 reg = <0x0 0x7A0000>; [all …]
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H A D | t2080rdb.dts | 46 reg = <0xf 0xfe0c0000 0 0x11000>; 49 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 52 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 91 reg = <0x1>; 94 reg = <0x2>; 101 reg = <0xc>; 106 reg = <0xd>; 109 xg_aq1202_phy3: ethernet-phy@0 { 111 reg = <0x0>; 116 reg = <0x1>;
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H A D | cyrus_p5020.dts | 30 size = <0 0x1000000>; 31 alignment = <0 0x1000000>; 34 size = <0 0x400000>; 35 alignment = <0 0x400000>; 38 size = <0 0x2000000>; 39 alignment = <0 0x2000000>; 44 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 48 ranges = <0x0 0xf 0xf4000000 0x200000>; 52 ranges = <0x0 0xf 0xf4200000 0x200000>; 56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | oca4080.dts | 58 size = <0 0x1000000>; 59 alignment = <0 0x1000000>; 62 size = <0 0x400000>; 63 alignment = <0 0x400000>; 66 size = <0 0x2000000>; 67 alignment = <0 0x2000000>; 72 ranges = <0x00000000 0xf 0x00000000 0x01008000>; 76 ranges = <0x0 0xf 0xf4000000 0x200000>; 80 ranges = <0x0 0xf 0xf4200000 0x200000>; 84 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; [all …]
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H A D | interlaken-lac-portals.dtsi | 34 #address-cells = <0x1>; 35 #size-cells = <0x1>; 38 lportal0: lac-portal@0 { 39 compatible = "fsl,interlaken-lac-portal-v1.0"; 40 reg = <0x0 0x1000>; 44 compatible = "fsl,interlaken-lac-portal-v1.0"; 45 reg = <0x1000 0x1000>; 49 compatible = "fsl,interlaken-lac-portal-v1.0"; 50 reg = <0x2000 0x1000>; 54 compatible = "fsl,interlaken-lac-portal-v1.0"; [all …]
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H A D | p5020si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 52 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 67 fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */ 68 pcie@0 { 69 reg = <0 0 0 0 0>; 75 interrupt-map-mask = <0xf800 0 0 7>; [all …]
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H A D | p5040si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 52 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 67 pcie@0 { 68 reg = <0 0 0 0 0>; 74 interrupt-map-mask = <0xf800 0 0 7>; 76 /* IDSEL 0x0 */ [all …]
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H A D | c293si-post.dtsi | 39 interrupts = <19 2 0 0>; 42 /* controller at 0xa000 */ 48 bus-range = <0 255>; 50 interrupts = <16 2 0 0>; 52 pcie@0 { 53 reg = <0 0 0 0 0>; 58 interrupts = <16 2 0 0>; 59 interrupt-map-mask = <0xf800 0 0 7>; 61 /* IDSEL 0x0 */ 62 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0x0 0x0 [all …]
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H A D | t2080qds.dts | 52 reg = <0xf 0xfe0c0000 0 0x11000>; 55 ranges = <0 0 0xc 0x20000000 0 0x10000000>; 58 ranges = <0 0 0xc 0x30000000 0 0x10000000>; 108 reg = <0x3>; 119 #size-cells = <0>; 120 reg = <0x54 1>; 121 mux-mask = <0xe0>; 123 t2080mdio0: mdio@0 { 125 #size-cells = <0>; 126 reg = <0>; [all …]
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/linux/drivers/reset/ |
H A D | reset-qcom-aoss.c | 30 [AOSS_CC_MSS_RESTART] = {0x10000}, 31 [AOSS_CC_CAMSS_RESTART] = {0x11000}, 32 [AOSS_CC_VENUS_RESTART] = {0x12000}, 33 [AOSS_CC_GPU_RESTART] = {0x13000}, 34 [AOSS_CC_DISPSS_RESTART] = {0x14000}, 35 [AOSS_CC_WCSS_RESTART] = {0x20000}, 36 [AOSS_CC_LPASS_RESTART] = {0x30000}, 59 return 0; in qcom_aoss_control_assert() 68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert() 71 return 0; in qcom_aoss_control_deassert() [all …]
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/linux/arch/mips/include/asm/sn/sn0/ |
H A D | kldir.h | 28 * 0x2000000 (32M) +-----------------------------------------+ 30 * 0x1F80000 (31.5M) +-----------------------------------------+ 32 * 0x1C00000 (30M) +-----------------------------------------+ 34 * 0x0800000 (28M) +-----------------------------------------+ 36 * 0x1B00000 (27M) +-----------------------------------------+ 38 * 0x1A00000 (26M) +-----------------------------------------+ 40 * 0x1800000 (24M) +-----------------------------------------+ 42 * 0x1600000 (22M) +-----------------------------------------+ 48 * 0x190000 (2M--) +-----------------------------------------+ 51 * 0x34000 (208K) +-----------------------------------------+ [all …]
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/linux/arch/arm/mach-imx/ |
H A D | mx2x.h | 16 #define MX2x_AIPI_BASE_ADDR 0x10000000 18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) 19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) 20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000) 21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000) 22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000) 23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000) 24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000) 25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000) 26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000) [all …]
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/linux/arch/arm/mach-dove/ |
H A D | dove.h | 14 * e0000000 @runtime 128M PCIe-0 Memory space 18 * f2000000 fee00000 1M PCIe-0 I/O space 22 #define DOVE_CESA_PHYS_BASE 0xc8000000 23 #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) 26 #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 29 #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 32 #define DOVE_BOOTROM_PHYS_BASE 0xf8000000 35 #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 36 #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) 39 #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 [all …]
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