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/linux/drivers/media/pci/mgb4/
H A Dmgb4_cmt.c19 …{0x1208, 0x0000, 0x171C, 0x0000, 0x1E38, 0x0000, 0x11C7, 0x0000, 0x1041, 0x01BC, 0x7C01, 0x7DE9, 0…
20 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x130D, 0x0080, 0x0041, 0x0090, 0x7C01, 0x7DE9, 0…
21 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x165A, 0x0080, 0x0082, 0x00FA, 0x7C01, 0x7DE9, 0…
22 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x1187, 0x0080, 0x1041, 0x01EE, 0x7C01, 0x7DE9, 0…
23 …{0x1186, 0x0000, 0x1555, 0x0000, 0x1AAA, 0x0000, 0x1451, 0x0000, 0x0042, 0x0013, 0x7C01, 0x7DE9, 0…
24 …{0x11C7, 0x0000, 0x1619, 0x0080, 0x1C71, 0x0000, 0x134E, 0x0080, 0x0041, 0x005E, 0x7C01, 0x7DE9, 0…
25 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x1619, 0x0080, 0x0083, 0x00FA, 0x7C01, 0x7DE9, 0…
26 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x179E, 0x0000, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
27 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x179F, 0x0080, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
28 …{0x1145, 0x0000, 0x1452, 0x0080, 0x18E3, 0x0000, 0x17DF, 0x0000, 0x00C3, 0x00FA, 0x7C01, 0x7DE9, 0…
[all …]
/linux/Documentation/admin-guide/media/
H A Drkisp1.rst77 YUV4:2:2 -> YUV4:2:0). They also have cropping capability on the sink pad.
86 This is the isp entity. It is connected to the sensor on sink pad 0 and
88 the CSI-2 protocol. It has a cropping capability on sink pad 0 that is
90 Cropping on sink pad 0 defines the image region from the sensor.
133 In the following example, the sensor connected to pad 0 of 'rkisp1_isp' is
144 "media-ctl" "-d" "platform:rkisp1" "-l" "'imx219 4-0010':0 -> 'rkisp1_isp':0 [1]"
145 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_selfpath':0 [1]"
146 "media-ctl" "-d" "platform:rkisp1" "-l" "'rkisp1_isp':2 -> 'rkisp1_resizer_mainpath':0 [0]"
148 # set format for imx219 4-0010:0
149 "media-ctl" "-d" "platform:rkisp1" "--set-v4l2" '"imx219 4-0010":0 [fmt:SRGGB10_1X10/1640x1232]'
[all …]
/linux/arch/m68k/mac/
H A Dpsc.c47 for (i = 0x30 ; i < 0x70 ; i += 0x10) { in psc_debug_dump()
48 printk(KERN_DEBUG "PSC #%d: IFR = 0x%02X IER = 0x%02X\n", in psc_debug_dump()
65 for (i = 0 ; i < 9 ; i++) { in psc_dma_die_die_die()
66 psc_write_word(PSC_CTL_BASE + (i << 4), 0x8800); in psc_dma_die_die_die()
67 psc_write_word(PSC_CTL_BASE + (i << 4), 0x1000); in psc_dma_die_die_die()
68 psc_write_word(PSC_CMD_BASE + (i << 5), 0x1100); in psc_dma_die_die_die()
69 psc_write_word(PSC_CMD_BASE + (i << 5) + 0x10, 0x1100); in psc_dma_die_die_die()
107 for (i = 0x30 ; i < 0x70 ; i += 0x10) { in psc_init()
108 psc_write_byte(pIERbase + i, 0x0F); in psc_init()
109 psc_write_byte(pIFRbase + i, 0x0F); in psc_init()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dnv40.c27 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
33 case 0x43: in nv40_sensor_style()
34 case 0x44: in nv40_sensor_style()
35 case 0x4a: in nv40_sensor_style()
36 case 0x47: in nv40_sensor_style()
38 case 0x46: in nv40_sensor_style()
39 case 0x49: in nv40_sensor_style()
40 case 0x4b: in nv40_sensor_style()
41 case 0x4e: in nv40_sensor_style()
42 case 0x4c: in nv40_sensor_style()
[all …]
H A Dg84.c34 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) in g84_temp_get()
35 return nvkm_rd32(device, 0x20400); in g84_temp_get()
46 if (nvkm_fuse_read(device->fuse, 0x1a8) == 1) { in g84_sensor_setup()
47 nvkm_mask(device, 0x20008, 0x80008000, 0x80000000); in g84_sensor_setup()
48 nvkm_mask(device, 0x2000c, 0x80000003, 0x00000000); in g84_sensor_setup()
63 /* enable RISING and FALLING IRQs for shutdown, THRS 0, 1, 2 and 4 */ in g84_therm_program_alarms()
64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
27 apahb_gate: apahb-gate@0 {
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
42 pmu_gate: pmu-gate@0 {
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dcdns,dphy-rx.yaml21 const: 0
39 reg = <0x4580000 0x1100>;
40 #phy-cells = <0>;
/linux/drivers/net/ethernet/synopsys/
H A Ddwc-xlgmac-reg.h22 #define MAC_TCR 0x0000
23 #define MAC_RCR 0x0004
24 #define MAC_PFR 0x0008
25 #define MAC_HTR0 0x0010
26 #define MAC_VLANTR 0x0050
27 #define MAC_VLANHTR 0x0058
28 #define MAC_VLANIR 0x0060
29 #define MAC_Q0TFCR 0x0070
30 #define MAC_RFCR 0x0090
31 #define MAC_RQC0R 0x00a0
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Dqcom,usb-vbus-regulator.yaml49 #size-cells = <0>;
53 reg = <0x1100>;
/linux/arch/arm/mach-omap2/
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
H A Dcm2_44xx.h26 #define OMAP4430_CM2_BASE 0x4a008000
32 #define OMAP4430_CM2_OCP_SOCKET_INST 0x0000
33 #define OMAP4430_CM2_CKGEN_INST 0x0100
34 #define OMAP4430_CM2_ALWAYS_ON_INST 0x0600
35 #define OMAP4430_CM2_CORE_INST 0x0700
36 #define OMAP4430_CM2_IVAHD_INST 0x0f00
37 #define OMAP4430_CM2_CAM_INST 0x1000
38 #define OMAP4430_CM2_DSS_INST 0x1100
39 #define OMAP4430_CM2_GFX_INST 0x1200
40 #define OMAP4430_CM2_L3INIT_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
H A Dprm33xx.h14 #define AM33XX_PRM_BASE 0x44E00000
21 #define AM33XX_PRM_OCP_SOCKET_MOD 0x0B00
22 #define AM33XX_PRM_PER_MOD 0x0C00
23 #define AM33XX_PRM_WKUP_MOD 0x0D00
24 #define AM33XX_PRM_MPU_MOD 0x0E00
25 #define AM33XX_PRM_DEVICE_MOD 0x0F00
26 #define AM33XX_PRM_RTC_MOD 0x1000
27 #define AM33XX_PRM_GFX_MOD 0x1100
28 #define AM33XX_PRM_CEFUSE_MOD 0x1200
31 #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/linux/arch/sparc/include/asm/
H A Dcontregs.h12 #define AC_M_PCR 0x0000 /* shv Processor Control Reg */
13 #define AC_M_CTPR 0x0100 /* shv Context Table Pointer Reg */
14 #define AC_M_CXR 0x0200 /* shv Context Register */
15 #define AC_M_SFSR 0x0300 /* shv Synchronous Fault Status Reg */
16 #define AC_M_SFAR 0x0400 /* shv Synchronous Fault Address Reg */
17 #define AC_M_AFSR 0x0500 /* hv Asynchronous Fault Status Reg */
18 #define AC_M_AFAR 0x0600 /* hv Asynchronous Fault Address Reg */
19 #define AC_M_RESET 0x0700 /* hv Reset Reg */
20 #define AC_M_RPR 0x1000 /* hv Root Pointer Reg */
21 #define AC_M_TSUTRCR 0x1000 /* s TLB Replacement Ctrl Reg */
[all …]
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux/drivers/net/wan/
H A Dslic_ds26522.h10 #define DS26522_RF_ADDR_START 0x00
11 #define DS26522_RF_ADDR_END 0xef
12 #define DS26522_GLB_ADDR_START 0xf0
13 #define DS26522_GLB_ADDR_END 0xff
14 #define DS26522_TF_ADDR_START 0x100
15 #define DS26522_TF_ADDR_END 0x1ef
16 #define DS26522_LIU_ADDR_START 0x1000
17 #define DS26522_LIU_ADDR_END 0x101f
18 #define DS26522_TEST_ADDR_START 0x1008
19 #define DS26522_TEST_ADDR_END 0x101f
[all …]
/linux/drivers/video/fbdev/
H A Dsmscufx.c35 ({ if (status < 0) pr_warn(fmt, ##args); })
38 ({ if (status < 0) { pr_warn(fmt, ##args); return status; } })
41 ({ if (status < 0) { pr_warn(fmt, ##args); goto error; } })
45 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
46 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
55 #define UFX_IOCTL_RETURN_EDID (0xAD)
56 #define UFX_IOCTL_REPORT_DAMAGE (0xAA)
100 atomic_t usb_active; /* 0 = update virtual buffer, but no usb traffic */
111 .xpanstep = 0,
112 .ypanstep = 0,
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dmediatek,mtk-ahci.yaml80 reg = <0x1a200000 0x1100>;
91 ports-implemented = <0x1>;
/linux/arch/arm64/boot/dts/qcom/
H A Dpm4125.dtsi12 pmic@0 {
14 reg = <0x0 SPMI_USID>;
16 #size-cells = <0>;
20 reg = <0x800>;
24 interrupts-extended = <&spmi_bus 0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
32 interrupts-extended = <&spmi_bus 0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
41 reg = <0x1100>;
47 reg = <0x1500>;
48 interrupts = <0x0 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
49 <0x0 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
[all …]
/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_model.h32 input->filter.formatted.src_ip[0] = (__force __be32)val; in ixgbe_mat_prgm_sip()
33 mask->formatted.src_ip[0] = (__force __be32)m; in ixgbe_mat_prgm_sip()
34 return 0; in ixgbe_mat_prgm_sip()
41 input->filter.formatted.dst_ip[0] = (__force __be32)val; in ixgbe_mat_prgm_dip()
42 mask->formatted.dst_ip[0] = (__force __be32)m; in ixgbe_mat_prgm_dip()
43 return 0; in ixgbe_mat_prgm_dip()
58 input->filter.formatted.src_port = (__force __be16)(val & 0xffff); in ixgbe_mat_prgm_ports()
59 mask->formatted.src_port = (__force __be16)(m & 0xffff); in ixgbe_mat_prgm_ports()
63 return 0; in ixgbe_mat_prgm_ports()
67 {.off = 0, .val = ixgbe_mat_prgm_ports,
[all …]
/linux/arch/m68k/include/asm/
H A Dcontregs.h15 #define AC_IDPROM 0x00000000 /* 34 ID PROM, R/O, byte, 32 bytes */
16 #define AC_PAGEMAP 0x10000000 /* 3 Pagemap R/W, long */
17 #define AC_SEGMAP 0x20000000 /* 3 Segment map, byte */
18 #define AC_CONTEXT 0x30000000 /* 34c current mmu-context */
19 #define AC_SENABLE 0x40000000 /* 34c system dvma/cache/reset enable reg*/
20 #define AC_UDVMA_ENB 0x50000000 /* 34 Not used on Sun boards, byte */
21 #define AC_BUS_ERROR 0x60000000 /* 34 Not cleared on read, byte. */
22 #define AC_SYNC_ERR 0x60000000 /* c fault type */
23 #define AC_SYNC_VA 0x60000004 /* c fault virtual address */
24 #define AC_ASYNC_ERR 0x60000008 /* c asynchronous fault type */
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dqcom,pon.yaml123 reg = <0x0c440000 0x1100>;
125 #size-cells = <0>;
127 pmic@0 {
128 reg = <0x0 SPMI_USID>;
130 #size-cells = <0>;
134 reg = <0x800>;
138 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
146 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
/linux/include/linux/mmc/
H A Dsdio_ids.h13 #define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */
14 #define SDIO_CLASS_UART 0x01 /* standard UART interface */
15 #define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */
16 #define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */
17 #define SDIO_CLASS_GPS 0x04 /* GPS standard interface */
18 #define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */
19 #define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
20 #define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
21 #define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
22 #define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
[all …]
/linux/drivers/devfreq/event/
H A Dexynos-ppmu.h13 PPMU_DISABLE = 0,
18 PPMU_PMNCNT0 = 0,
30 PPMU_RO_BUSY_CYCLE_CNT = 0x0,
31 PPMU_WO_BUSY_CYCLE_CNT = 0x1,
32 PPMU_RW_BUSY_CYCLE_CNT = 0x2,
33 PPMU_RO_REQUEST_CNT = 0x3,
34 PPMU_WO_REQUEST_CNT = 0x4,
35 PPMU_RO_DATA_CNT = 0x5,
36 PPMU_WO_DATA_CNT = 0x6,
37 PPMU_RO_LATENCY = 0x12,
[all …]

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