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/linux/tools/testing/selftests/bpf/verifier/
H A Datomic_and.c4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_and(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x010) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x010, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
H A Datomic_xor.c4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_xor(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x101) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x101, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
H A Datomic_or.c4 /* val = 0x110; */
5 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
6 /* atomic_or(&val, 0x011); */
7 BPF_MOV64_IMM(BPF_REG_1, 0x011),
9 /* if (val != 0x111) exit(2); */
11 BPF_JMP_IMM(BPF_JEQ, BPF_REG_0, 0x111, 2),
15 BPF_MOV64_IMM(BPF_REG_0, 0),
16 BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 0x011, 1),
26 /* val = 0x110; */
27 BPF_ST_MEM(BPF_DW, BPF_REG_10, -8, 0x110),
[all …]
/linux/tools/testing/selftests/bpf/progs/
H A Darena_atomics.c17 __ulong(map_extra, 0x1ull << 32); /* start of mmap() region */
19 __ulong(map_extra, 0x1ull << 44); /* start of mmap() region */
38 __u32 pid = 0; in add()
41 __u64 __arena_global add64_result = 0; in add()
43 __u32 __arena_global add32_result = 0; in add()
44 __u64 __arena_global add_stack_value_copy = 0; in add()
45 __u64 __arena_global add_stack_result = 0; in add()
52 return 0; in add()
63 return 0;
67 __s64 __arena_global sub64_result = 0; in sub()
[all...]
H A Datomics.c13 __u32 pid = 0;
16 __u64 add64_result = 0;
18 __u32 add32_result = 0;
19 __u64 add_stack_value_copy = 0;
20 __u64 add_stack_result = 0;
27 return 0; in add()
38 return 0; in add()
42 __s64 sub64_result = 0;
44 __s32 sub32_result = 0;
45 __s64 sub_stack_value_copy = 0;
[all …]
/linux/arch/mips/include/asm/
H A Dhpet.h9 #define HPET_ID 0x000
10 #define HPET_PERIOD 0x004
11 #define HPET_CFG 0x010
12 #define HPET_STATUS 0x020
13 #define HPET_COUNTER 0x0f0
15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
19 #define HPET_T0_IRS 0x001
20 #define HPET_T1_IRS 0x002
[all …]
/linux/drivers/media/i2c/cx25840/
H A Dcx25840-audio.c39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq()
40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq()
42 cx25840_write4(client, 0x108, 0x1006040f); in cx25840_set_audclk_freq()
45 * VID_PLL Fraction (register 0x10c) = 0x2be2fe in cx25840_set_audclk_freq()
46 * 28636360 * 0xf.15f17f0/4 = 108 MHz in cx25840_set_audclk_freq()
51 * AUX_PLL Fraction = 0x1bb39ee in cx25840_set_audclk_freq()
52 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384 in cx25840_set_audclk_freq()
57 cx25840_write4(client, 0x110, 0x01bb39ee); in cx25840_set_audclk_freq()
61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq()
63 cx25840_write(client, 0x127, 0x50); in cx25840_set_audclk_freq()
[all …]
/linux/Documentation/translations/zh_CN/core-api/
H A Dprintk-formats.rst115 %pS versatile_init+0x0/0x110
117 %pSR versatile_init+0x9/0x110
119 %pB prev_fn_of_versatile_init+0x88/0x88
133 %pS versatile_init+0x0/0x110 [module_name]
134 %pSb versatile_init+0x0/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
135 %pSRb versatile_init+0x9/0x110 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
137 %pBb prev_fn_of_versatile_init+0x88/0x88 [module_name ed5019fdf5e53be37cb1ba7899292d7e143b259e]
195 %pr [mem 0x60000000-0x6fffffff flags 0x2200] or
196 [mem 0x0000000060000000-0x000000006fffffff flags 0x2200]
197 %pR [mem 0x60000000-0x6fffffff pref] or
[all …]
/linux/arch/x86/include/asm/
H A Dhpet.h11 #define HPET_ID 0x000
12 #define HPET_PERIOD 0x004
13 #define HPET_CFG 0x010
14 #define HPET_STATUS 0x020
15 #define HPET_COUNTER 0x0f0
17 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
18 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
19 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
21 #define HPET_T0_CFG 0x100
22 #define HPET_T0_CMP 0x108
[all …]
/linux/arch/sparc/include/asm/
H A Dcompat.h24 #define COMPAT_RLIM_INFINITY 0x7fffffff
28 #define COMPAT_UTS_MACHINE "sparc\0\0"
154 /* Vector 0x110 is LINUX_32BIT_SYSCALL_TRAP */ in in_compat_syscall()
155 return pt_regs_trap_type(current_pt_regs()) == 0x110; in in_compat_syscall()
/linux/tools/testing/selftests/bpf/prog_tests/
H A Datomics.c70 ASSERT_EQ(skel->data->and64_value, 0x010ull << 32, "and64_value"); in test_and()
71 ASSERT_EQ(skel->bss->and64_result, 0x110ull << 32, "and64_result"); in test_and()
73 ASSERT_EQ(skel->data->and32_value, 0x010, "and32_value"); in test_and()
74 ASSERT_EQ(skel->bss->and32_result, 0x110, "and32_result"); in test_and()
76 ASSERT_EQ(skel->data->and_noreturn_value, 0x010ull << 32, "and_noreturn_value"); in test_and()
92 ASSERT_EQ(skel->data->or64_value, 0x111ull << 32, "or64_value"); in test_or()
93 ASSERT_EQ(skel->bss->or64_result, 0x110ull << 32, "or64_result"); in test_or()
95 ASSERT_EQ(skel->data->or32_value, 0x111, "or32_value"); in test_or()
96 ASSERT_EQ(skel->bss->or32_result, 0x11 in test_or()
[all...]
/linux/drivers/media/usb/stk1160/
H A Dstk1160-reg.h14 #define STK1160_GCTRL 0x000
17 #define STK1160_RMCTL 0x00c
20 #define STK1160_POSVA 0x010
21 #define STK1160_POSV_L 0x010
22 #define STK1160_POSV_M 0x011
23 #define STK1160_POSV_H 0x012
30 * with bit #7 (0x?? OR 0x80 to activate).
32 #define STK1160_DCTRL 0x100
39 * Bit 0 - Horizontal Decimation Control
40 * 0 Horizontal decimation is disabled.
[all …]
/linux/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
/linux/Documentation/scsi/
H A Dadvansys.rst90 default the debug level is 0.
96 'deb' and the fourth hex digit specifies the debug level: 0 - F.
97 The following command line will look for an adapter at 0x330
100 linux advansys=0x330,0,0,0,0xdeb2
112 0 Errors Only
141 syscall(103, 7, 0, 0);
163 /proc/scsi/advansys/{0,1,2,3,...}
167 cat /proc/scsi/advansys/0
192 boot: linux advansys=0x0
198 linux advansys=0x110
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi4_core.h15 #define HDMI_CORE_SYS_VND_IDL 0x0
16 #define HDMI_CORE_SYS_DEV_IDL 0x8
17 #define HDMI_CORE_SYS_DEV_IDH 0xC
18 #define HDMI_CORE_SYS_DEV_REV 0x10
19 #define HDMI_CORE_SYS_SRST 0x14
20 #define HDMI_CORE_SYS_SYS_CTRL1 0x20
21 #define HDMI_CORE_SYS_SYS_STAT 0x24
22 #define HDMI_CORE_SYS_SYS_CTRL3 0x28
23 #define HDMI_CORE_SYS_DCTL 0x34
24 #define HDMI_CORE_SYS_DE_DLY 0xC8
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dclock.json8 "EventCode": "0x101",
14 "EventCode": "0x110",
/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-sys-s3c64xx.h16 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
18 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
20 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
22 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183-kukui-kodama-sku272.dts5 * SKU: 0x110 => 272
7 * - bits 7..4: Panel ID: 0x1 (AUO)
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_tdshp.h10 #define MDP_HIST_CFG_00 (0x064)
11 #define MDP_HIST_CFG_01 (0x068)
12 #define MDP_TDSHP_CTRL (0x100)
13 #define MDP_TDSHP_CFG (0x110)
14 #define MDP_TDSHP_INPUT_SIZE (0x120)
15 #define MDP_TDSHP_OUTPUT_OFFSET (0x124)
16 #define MDP_TDSHP_OUTPUT_SIZE (0x128)
17 #define MDP_LUMA_HIST_INIT (0x200)
18 #define MDP_DC_TWO_D_W1_RESULT_INIT (0x260)
19 #define MDP_CONTOUR_HIST_INIT (0x398)
[all …]

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