/linux/drivers/media/usb/gspca/ |
H A D | sn9c2028.c | 37 unsigned char to_read; /* length to read. 0 means no reply requested */ 46 .priv = 0}, 55 .priv = 0}, 64 command[0], command[1], command[2], in sn9c2028_command() 69 usb_sndctrlpipe(gspca_dev->dev, 0), in sn9c2028_command() 72 2, 0, gspca_dev->usb_buf, 6, 500); in sn9c2028_command() 73 if (rc < 0) { in sn9c2028_command() 75 gspca_dev->usb_buf[0], rc); in sn9c2028_command() 79 return 0; in sn9c2028_command() 87 usb_rcvctrlpipe(gspca_dev->dev, 0), in sn9c2028_read1() [all …]
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H A D | conex.c | 53 .priv = 0}, 69 usb_rcvctrlpipe(dev, 0), in reg_r() 70 0, in reg_r() 72 0, in reg_r() 76 index, gspca_dev->usb_buf[0]); in reg_r() 86 gspca_dev->usb_buf[0] = val; in reg_w_val() 88 usb_sndctrlpipe(dev, 0), in reg_w_val() 89 0, in reg_w_val() 91 0, in reg_w_val() 111 usb_sndctrlpipe(dev, 0), in reg_w() [all …]
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H A D | nw80x.c | 159 * - 3rd byte: data length (=0 for end of sequence) 162 #define I2C0 0xff 165 0x04, 0x05, 0x01, 0x61, 166 0x04, 0x04, 0x01, 0x01, 167 0x04, 0x06, 0x01, 0x04, 168 0x04, 0x04, 0x03, 0x00, 0x00, 0x00, 169 0x05, 0x05, 0x01, 0x00, 170 0, 0, 0 173 0x04, 0x06, 0x01, 0xc0, 174 0x00, 0x00, 0x40, 0x10, 0x43, 0x00, 0xb4, 0x01, 0x10, 0x00, 0x4f, [all …]
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H A D | jpeg.h | 20 0xff, 0xd8, /* jpeg */ 23 0xff, 0xdb, 0x00, 0x84, /* DQT */ 24 0, 26 0x10, 0x0b, 0x0c, 0x0e, 0x0c, 0x0a, 0x10, 0x0e, 27 0x0d, 0x0e, 0x12, 0x11, 0x10, 0x13, 0x18, 0x28, 28 0x1a, 0x18, 0x16, 0x16, 0x18, 0x31, 0x23, 0x25, 29 0x1d, 0x28, 0x3a, 0x33, 0x3d, 0x3c, 0x39, 0x33, 30 0x38, 0x37, 0x40, 0x48, 0x5c, 0x4e, 0x40, 0x44, 31 0x57, 0x45, 0x37, 0x38, 0x50, 0x6d, 0x51, 0x57, 32 0x5f, 0x62, 0x67, 0x68, 0x67, 0x3e, 0x4d, 0x71, [all …]
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H A D | pac7311.c | 14 * 0x08 Unknown compressor related, must always be 8 except when not 16 * 0x1b Auto white balance related, bit 0 is AWB enable (inverted) 18 * 0x78 Global control, bit 6 controls the LED (inverted) 19 * 0x80 Compression balance, interesting settings: 20 * 0x01 Use this to allow the camera to switch to higher compr. 22 * 0x1c From usb captures under Windows for 640x480 23 * 0x2a Values >= this switch the camera to a lower compression, 29 * 0x3f From usb captures under Windows for 320x240 30 * 0x69 From usb captures under Windows for 160x120 35 * 0x02 Clock divider 2-63, fps =~ 60 / val. Must be a multiple of 3 on [all …]
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx7d-cl-som-imx7.dts | 8 * of the GPL or the X11 license, at your option. Note that this dual 23 reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ 46 pinctrl-0 = <&pinctrl_enet1>; 50 assigned-clock-rates = <0>, <100000000>; 58 #size-cells = <0>; 60 ethphy0: ethernet-phy@0 { 62 reg = <0>; 74 pinctrl-0 = <&pinctrl_enet2>; 78 assigned-clock-rates = <0>, <100000000>; 87 pinctrl-0 = <&pinctrl_i2c2>; [all …]
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
H A D | mxm.c | 36 return 0x0000; in mxm_table() 43 return 0x0000; in mxm_table() 55 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, 56 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 60 0x00, 0x12, 0x22, 0x11, 0x32, 0x31, 0x11, 0x31, 61 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 65 0x00, 0x14, 0x24, 0x11, 0x34, 0x31, 0x11, 0x31, 66 0x11, 0x31, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00 70 0x00, 0x14, 0x12, 0x11, 0x00, 0x31, 0x11, 0x31, 71 0x11, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 [all …]
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/linux/arch/arm/crypto/ |
H A D | chacha-scalar-core.S | 14 * (x8, x9) to the stack and swap them out with (x10, x11). This adds one 24 * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such 38 X9_X11 .req r9 // shared by x9 and x11 109 // save (x8, x9); restore (x10, x11) 110 __strd X8_X10, X9_X11, sp, 0 113 // quarterrounds: (x2, x6, x10, x14) and (x3, x7, x11, x15) 121 // quarterrounds: (x0, x5, x10, x15) and (x1, x6, x11, x12) 124 // save (x10, x11); restore (x8, x9) 126 __ldrd X8_X10, X9_X11, sp, 0 133 .set brot, 0 [all …]
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/linux/drivers/video/fbdev/ |
H A D | platinumfb.h | 54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5)) 55 * Newer ones use the values in clocksel[0], for which the formula 57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5)) 69 #define DIV2 0x20 70 #define DIV4 0x40 71 #define DIV8 0x60 72 #define DIV16 0x80 76 0x5c00, 78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0, 79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d, [all …]
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/linux/drivers/media/pci/solo6x10/ |
H A D | solo6x10-tw28.c | 30 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x00 */ 31 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f, 32 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x10 */ 33 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f, 34 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x20 */ 35 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f, 36 0x00, 0xf0, 0x70, 0x30, 0x80, 0x80, 0x00, 0x02, /* 0x30 */ 37 0x12, 0xf5, 0x0c, 0xd0, 0x00, 0x00, 0x00, 0x7f, 38 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x40 */ 39 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, [all …]
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/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3288-veyron-jerry.dts | 25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; 45 #size-cells = <0>; 52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f 56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c [all …]
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/linux/arch/x86/lib/ |
H A D | crc32-pclmul.S | 7 * CRC32 polynomial:0x04c11db7(BE)/0xEDB88320(LE) 24 * [x4*128+32 mod P(x) << 32)]' << 1 = 0x154442bd4 25 * #define CONSTANT_R1 0x154442bd4LL 27 * [(x4*128-32 mod P(x) << 32)]' << 1 = 0x1c6e41596 28 * #define CONSTANT_R2 0x1c6e41596LL 31 .octa 0x00000001c6e415960000000154442bd4 33 * [(x128+32 mod P(x) << 32)]' << 1 = 0x1751997d0 34 * #define CONSTANT_R3 0x1751997d0LL 36 * [(x128-32 mod P(x) << 32)]' << 1 = 0x0ccaa009e 37 * #define CONSTANT_R4 0x0ccaa009eLL [all …]
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/linux/arch/powerpc/boot/dts/fsl/ |
H A D | p2020ds.dtsi | 36 nor@0,0 { 40 reg = <0x0 0x0 0x8000000>; 44 ramdisk@0 { 45 reg = <0x0 0x03000000>; 50 reg = <0x03000000 0x00e00000>; 55 reg = <0x03e00000 0x00200000>; 60 reg = <0x04000000 0x00400000>; 65 reg = <0x04400000 0x03b00000>; 69 reg = <0x07f00000 0x00080000>; 74 reg = <0x07f80000 0x00080000>; [all …]
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H A D | mpc8572ds.dtsi | 36 nor@0,0 { 40 reg = <0x0 0x0 0x8000000>; 44 partition@0 { 45 reg = <0x0 0x03000000>; 50 reg = <0x03000000 0x00e00000>; 56 reg = <0x03e00000 0x00200000>; 62 reg = <0x04000000 0x00400000>; 67 reg = <0x04400000 0x03b00000>; 72 reg = <0x07f00000 0x00060000>; 77 reg = <0x07f60000 0x00020000>; [all …]
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/linux/drivers/phy/starfive/ |
H A D | phy-jh7110-dphy-tx.c | 26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0 27 #define STF_DPHY_AON_POWER_READY_N BIT(0) 43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0) 45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0) 47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0) 54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0) 59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0) 64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0) 65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0) 100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d}, [all …]
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/linux/fs/unicode/ |
H A D | utf8data.c_shipped | 8 0, 9 0x10100, 10 0x20000, 11 0x20100, 12 0x30000, 13 0x30100, 14 0x30200, 15 0x40000, 16 0x40100, 17 0x50000, [all …]
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/linux/arch/mips/boot/dts/cavium-octeon/ |
H A D | octeon_3xxx.dts | 13 soc@0 { 15 phy0: ethernet-phy@0 { 19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ 21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ 23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ 24 reg = <0>; 31 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */ 33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */ 35 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */ 42 marvell,reg-init = <3 0x10 0 0x5777>, [all …]
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H A D | octeon_68xx.dts | 16 soc@0 { 26 * 1) Controller register (0 or 7) 27 * 2) Bit within the register (0..63) 29 #address-cells = <0>; 31 reg = <0x10701 0x00000000 0x0 0x4000000>; 37 reg = <0x10700 0x00000800 0x0 0x100>; 40 * 1) GPIO pin number (0..15) 49 interrupts = <7 0>, <7 1>, <7 2>, <7 3>, 58 #size-cells = <0>; 59 reg = <0x11800 0x00003800 0x0 0x40>; [all …]
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/linux/drivers/scsi/ |
H A D | scsi_lib_test.c | 21 .asc = 0x1, in scsi_lib_test_multiple_sense() 22 .ascq = 0x1, in scsi_lib_test_multiple_sense() 27 .asc = 0x11, in scsi_lib_test_multiple_sense() 28 .ascq = 0x0, in scsi_lib_test_multiple_sense() 34 .asc = 0x11, in scsi_lib_test_multiple_sense() 35 .ascq = 0x22, in scsi_lib_test_multiple_sense() 41 .asc = 0x11, in scsi_lib_test_multiple_sense() 54 .asc = 0x91, in scsi_lib_test_multiple_sense() 55 .ascq = 0x36, in scsi_lib_test_multiple_sense() 71 sc.result = 0; in scsi_lib_test_multiple_sense() [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
H A D | dpcs_3_0_0_sh_mask.h | 14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3 18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L 19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L 20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L 21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L 23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc 24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd [all …]
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H A D | dpcs_2_1_0_sh_mask.h | 27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L 32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L 33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L 34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L 36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc 37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd [all …]
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H A D | dpcs_2_0_0_sh_mask.h | 27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0 28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1 29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2 30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3 31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L 32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L 33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L 34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L 36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc 37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd [all …]
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/linux/drivers/net/wireless/realtek/rtl8xxxu/ |
H A D | 8192c.c | 21 .reg_0e00 = 0x07090c0c, 22 .reg_0e04 = 0x01020405, 23 .reg_0e08 = 0x00000000, 24 .reg_086c = 0x00000000, 26 .reg_0e10 = 0x0b0c0c0e, 27 .reg_0e14 = 0x01030506, 28 .reg_0e18 = 0x0b0c0d0e, 29 .reg_0e1c = 0x01030509, 31 .reg_0830 = 0x07090c0c, 32 .reg_0834 = 0x01020405, [all …]
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/linux/tools/testing/selftests/bpf/ |
H A D | ip_check_defrag_frags.h | 10 0x45, 0x0, 0x0, 0x2c, 0x0, 0x1, 0x20, 0x0, 0x40, 0x11, 11 0xac, 0xe8, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8, 12 0xbe, 0xee, 0xbe, 0xef, 0x0, 0x3a, 0x0, 0x0, 0x54, 0x48, 13 0x49, 0x53, 0x20, 0x49, 0x53, 0x20, 0x54, 0x48, 0x45, 0x20, 14 0x4f, 0x52, 0x49, 0x47, 17 0x45, 0x0, 0x0, 0x2c, 0x0, 0x1, 0x20, 0x3, 0x40, 0x11, 18 0xac, 0xe5, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8, 19 0x49, 0x4e, 0x41, 0x4c, 0x20, 0x4d, 0x45, 0x53, 0x53, 0x41, 20 0x47, 0x45, 0x2c, 0x20, 0x50, 0x4c, 0x45, 0x41, 0x53, 0x45, 21 0x20, 0x52, 0x45, 0x41, [all …]
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/linux/sound/pci/au88x0/ |
H A D | au8830.h | 18 #define NR_ADB 0x20 19 #define NR_SRC 0x10 20 #define NR_A3D 0x10 21 #define NR_MIXIN 0x20 22 #define NR_MIXOUT 0x10 23 #define NR_WT 0x40 26 #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */ 27 #define POS_MASK 0x00000fff 28 #define POS_SHIFT 0x0 29 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ [all …]
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