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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-main.dtsi11 reg = <0x00 0x67800000 0x00 0x00080000>,
12 <0x00 0x67e00000 0x00 0x0000c000>;
18 ti,sci-proc-ids = <0x33 0xff>;
24 reg = <0x00 0x02920000 0x00 0x1000>,
25 <0x00 0x02927000 0x00 0x400>,
26 <0x00 0x0e000000 0x00 0x00800000>,
27 <0x44 0x00000000 0x00 0x00001000>;
28 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
29 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
37 clocks = <&k3_clks 334 0>;
[all …]
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dti,j721e-pci-host.yaml78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
/linux/include/linux/comedi/
H A Dcomedi_pci.h19 #define PCI_VENDOR_ID_KOLTER 0x1001
20 #define PCI_VENDOR_ID_ICP 0x104c
21 #define PCI_VENDOR_ID_DT 0x1116
22 #define PCI_VENDOR_ID_IOTECH 0x1616
23 #define PCI_VENDOR_ID_CONTEC 0x1221
24 #define PCI_VENDOR_ID_RTD 0x1435
25 #define PCI_VENDOR_ID_HUMUSOFT 0x186c
/linux/Documentation/PCI/endpoint/function/binding/
H A Dpci-test.rst12 vendorid should be 0x104c
13 deviceid should be 0xb500 for DRA74x and 0xb501 for DRA72x
17 baseclass_code should be 0xff
H A Dpci-ntb.rst12 vendorid should be 0x104c
13 deviceid should be 0xb00d for TI's J721E SoC
16 subclass_code should be 0x00
17 baseclass_code should be 0x5
/linux/include/linux/mmc/
H A Dsdio_ids.h13 #define SDIO_CLASS_NONE 0x00 /* Not a SDIO standard interface */
14 #define SDIO_CLASS_UART 0x01 /* standard UART interface */
15 #define SDIO_CLASS_BT_A 0x02 /* Type-A BlueTooth std interface */
16 #define SDIO_CLASS_BT_B 0x03 /* Type-B BlueTooth std interface */
17 #define SDIO_CLASS_GPS 0x04 /* GPS standard interface */
18 #define SDIO_CLASS_CAMERA 0x05 /* Camera standard interface */
19 #define SDIO_CLASS_PHS 0x06 /* PHS standard interface */
20 #define SDIO_CLASS_WLAN 0x07 /* WLAN interface */
21 #define SDIO_CLASS_ATA 0x08 /* Embedded SDIO-ATA std interface */
22 #define SDIO_CLASS_BT_AMP 0x09 /* Type-A Bluetooth AMP interface */
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc-sm6375.c39 { 249600000, 2000000000, 0 },
44 .l = 0x20,
45 .alpha = 0x800,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329a299c,
49 .user_ctl_val = 0x00000001,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
55 .offset = 0x0,
[all …]
H A Ddispcc-sc7280.c34 { 249600000, 2000000000, 0 },
39 .l = 0x4F,
40 .alpha = 0x2AAA,
41 .config_ctl_val = 0x20485699,
42 .config_ctl_hi_val = 0x00002261,
43 .config_ctl_hi1_val = 0x329A299C,
44 .user_ctl_val = 0x00000001,
45 .user_ctl_hi_val = 0x00000805,
46 .user_ctl_hi1_val = 0x00000000,
50 .offset = 0x0,
[all …]
H A Dmmcc-msm8994.c44 { P_XO, 0 },
54 { P_XO, 0 },
64 { P_XO, 0 },
76 { P_XO, 0 },
91 { 1500000000, 2000000000, 0 },
95 { 500000000, 1500000000, 0 },
99 .post_div_mask = 0xf00,
103 .offset = 0x0,
108 .enable_reg = 0x100,
109 .enable_mask = BIT(0),
[all …]
H A Dmmcc-msm8998.c49 { 0x0, 1 },
50 { 0x1, 2 },
51 { 0x3, 4 },
52 { 0x7, 8 },
57 .offset = 0xc000,
60 .enable_reg = 0x1e0,
61 .enable_mask = BIT(0),
74 .offset = 0xc000,
89 .offset = 0xc050,
92 .enable_reg = 0x1e0,
[all …]
H A Dmmcc-msm8996.c64 { 1500000000, 2000000000, 0 },
70 { 1500000000, 2000000000, 0 },
74 { 500000000, 1500000000, 0 },
78 .offset = 0x0,
83 .enable_reg = 0x100,
84 .enable_mask = BIT(0),
97 .offset = 0x0,
112 .offset = 0x30,
117 .enable_reg = 0x100,
131 .offset = 0x30,
[all …]
/linux/Documentation/PCI/endpoint/
H A Dpci-ntb-howto.rst66 baseclass_code deviceid msi_interrupts pci-epf-ntb.0
73 vendorid with 0xffff and interrupt_pin with 0x0001::
76 0xffff
78 0x0001
88 # echo 0x104c > functions/pci_epf_ntb/func1/vendorid
89 # echo 0xb00d > functions/pci_epf_ntb/func1/deviceid
96 # ls functions/pci_epf_ntb/func1/pci_epf_ntb.0/
102 # echo 4 > functions/pci_epf_ntb/func1/pci_epf_ntb.0/db_count
103 # echo 128 > functions/pci_epf_ntb/func1/pci_epf_ntb.0/spad_count
104 # echo 2 > functions/pci_epf_ntb/func1/pci_epf_ntb.0/num_mws
[all …]
/linux/drivers/misc/mei/
H A Dhw-txe-regs.h30 #define PCI_CFG_TXE_FW_STS0 0x40
31 # define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK 0x0000000F
32 # define PCI_CFG_TXE_FW_STS0_OP_ST_MSK 0x000001C0
33 # define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
34 # define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK 0x0000F000
35 # define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK 0x000F0000
36 # define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK 0x00F00000
37 #define PCI_CFG_TXE_FW_STS1 0x48
39 #define IPC_BASE_ADDR 0x80400 /* SeC IPC Base Address */
42 #define SEC_IPC_INPUT_DOORBELL_REG (0x0000 + IPC_BASE_ADDR)
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/linux/arch/sh/include/asm/
H A Dhd64461.h10 * (please note manual reference 0x10000000 = 0xb0000000)
14 #define HD64461_PCC_WINDOW 0x01000000
16 /* Area 6 - Slot 0 - memory and/or IO card */
17 #define HD64461_IOBASE 0xb0000000
19 #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
20 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
21 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
22 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
25 #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
26 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-ice.dts18 reg = <0x00000008 0x00000000 0x00000000 0x20000000>;
28 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
128 <&pca9536 0 GPIO_ACTIVE_HIGH>;
129 linux,axis = <0>; /* ABS_X */
136 pinctrl-0 = <&user_leds>;
223 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
224 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
230 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
231 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
232 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dhw.h12 #define E1000_DEV_ID_82571EB_COPPER 0x105E
13 #define E1000_DEV_ID_82571EB_FIBER 0x105F
14 #define E1000_DEV_ID_82571EB_SERDES 0x1060
15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
21 #define E1000_DEV_ID_82572EI_COPPER 0x107D
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtn40.c28 tn40_write_reg(priv, TN40_REG_IMR, 0); in tn40_disable_interrupts()
39 memset(f, 0, sizeof(struct tn40_fifo)); in tn40_fifo_alloc()
53 f->rptr = 0; in tn40_fifo_alloc()
54 f->wptr = 0; in tn40_fifo_alloc()
60 return 0; in tn40_fifo_alloc()
83 for (i = 0; i < nelem; i++) in tn40_rxdb_alloc()
126 * takes 0 CPU cycles.
128 * Return: 0 on success and negative value on error.
166 return 0; in tn40_create_rx_ring()
186 for (i = 0; i < db->nelem; i++) { in tn40_rx_free_buffers()
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi-qp.h13 #define CORE_ID 0x0
14 #define VER_NUMBER 0x4
15 #define VER_TYPE 0x8
16 #define CONFIG_REG 0xc
19 #define CORE_TIMESTAMP_HHMM 0x14
20 #define CORE_TIMESTAMP_MMDD 0x18
21 #define CORE_TIMESTAMP_YYYY 0x1c
23 #define GLOBAL_SWRESET_REQUEST 0x40
26 #define GLOBAL_SWDISABLE 0x44
30 #define RESET_MANAGER_CONFIG0 0x48
[all …]
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c28 #define EXYNOS5_FSEL_9MHZ6 0x0
29 #define EXYNOS5_FSEL_10MHZ 0x1
30 #define EXYNOS5_FSEL_12MHZ 0x2
31 #define EXYNOS5_FSEL_19MHZ2 0x3
32 #define EXYNOS5_FSEL_20MHZ 0x4
33 #define EXYNOS5_FSEL_24MHZ 0x5
34 #define EXYNOS5_FSEL_26MHZ 0x6
35 #define EXYNOS5_FSEL_50MHZ 0x7
38 #define EXYNOS5_DRD_LINKSYSTEM 0x04
40 #define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
[all …]
/linux/drivers/net/ethernet/hisilicon/hns/
H A Dhns_dsaf_reg.h10 #define HNS_DEBUG_RING_IRQ_IDX 0
46 #define DSAF_SUB_SC_NT_SRAM_CLK_SEL_REG 0x100
47 #define DSAF_SUB_SC_HILINK3_CRG_CTRL0_REG 0x180
48 #define DSAF_SUB_SC_HILINK3_CRG_CTRL1_REG 0x184
49 #define DSAF_SUB_SC_HILINK3_CRG_CTRL2_REG 0x188
50 #define DSAF_SUB_SC_HILINK3_CRG_CTRL3_REG 0x18C
51 #define DSAF_SUB_SC_HILINK4_CRG_CTRL0_REG 0x190
52 #define DSAF_SUB_SC_HILINK4_CRG_CTRL1_REG 0x194
53 #define DSAF_SUB_SC_DSAF_CLK_EN_REG 0x300
54 #define DSAF_SUB_SC_DSAF_CLK_DIS_REG 0x304
[all …]

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