Lines Matching +full:0 +full:x104c
35 { 249600000, 2000000000, 0 },
40 .l = 0x4F,
41 .alpha = 0x2AAA,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002261,
44 .config_ctl_hi1_val = 0x329A299C,
45 .user_ctl_val = 0x00000001,
46 .user_ctl_hi_val = 0x00000805,
47 .user_ctl_hi1_val = 0x00000000,
51 .offset = 0x0,
68 { P_BI_TCXO, 0 },
76 { P_BI_TCXO, 0 },
88 { P_BI_TCXO, 0 },
98 { P_BI_TCXO, 0 },
110 { P_BI_TCXO, 0 },
124 { P_BI_TCXO, 0 },
134 { P_BI_TCXO, 0 },
144 F(19200000, P_BI_TCXO, 1, 0, 0),
145 F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
146 F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
151 .cmd_rcgr = 0x1170,
152 .mnd_width = 0,
165 .cmd_rcgr = 0x10d8,
166 .mnd_width = 0,
179 F(19200000, P_BI_TCXO, 1, 0, 0),
184 .cmd_rcgr = 0x1158,
185 .mnd_width = 0,
198 .cmd_rcgr = 0x1128,
199 .mnd_width = 0,
211 .cmd_rcgr = 0x110c,
212 .mnd_width = 0,
224 .cmd_rcgr = 0x1140,
237 .cmd_rcgr = 0x11d0,
238 .mnd_width = 0,
251 .cmd_rcgr = 0x11a0,
252 .mnd_width = 0,
265 .cmd_rcgr = 0x1188,
278 .cmd_rcgr = 0x10f4,
279 .mnd_width = 0,
292 F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
293 F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
294 F(380000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
295 F(506666667, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
296 F(608000000, P_DISP_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
301 .cmd_rcgr = 0x1090,
302 .mnd_width = 0,
315 .cmd_rcgr = 0x1078,
329 .cmd_rcgr = 0x10a8,
330 .mnd_width = 0,
343 .cmd_rcgr = 0x10c0,
344 .mnd_width = 0,
357 .reg = 0x10f0,
358 .shift = 0,
371 .reg = 0x1124,
372 .shift = 0,
385 .reg = 0x11b8,
386 .shift = 0,
399 .halt_reg = 0x1050,
402 .enable_reg = 0x1050,
403 .enable_mask = BIT(0),
417 .halt_reg = 0x1030,
420 .enable_reg = 0x1030,
421 .enable_mask = BIT(0),
435 .halt_reg = 0x1034,
438 .enable_reg = 0x1034,
439 .enable_mask = BIT(0),
453 .halt_reg = 0x104c,
456 .enable_reg = 0x104c,
457 .enable_mask = BIT(0),
471 .halt_reg = 0x1044,
474 .enable_reg = 0x1044,
475 .enable_mask = BIT(0),
489 .halt_reg = 0x103c,
492 .enable_reg = 0x103c,
493 .enable_mask = BIT(0),
507 .halt_reg = 0x1040,
510 .enable_reg = 0x1040,
511 .enable_mask = BIT(0),
525 .halt_reg = 0x1048,
528 .enable_reg = 0x1048,
529 .enable_mask = BIT(0),
543 .halt_reg = 0x1060,
546 .enable_reg = 0x1060,
547 .enable_mask = BIT(0),
561 .halt_reg = 0x1058,
564 .enable_reg = 0x1058,
565 .enable_mask = BIT(0),
579 .halt_reg = 0x105c,
582 .enable_reg = 0x105c,
583 .enable_mask = BIT(0),
597 .halt_reg = 0x1054,
600 .enable_reg = 0x1054,
601 .enable_mask = BIT(0),
615 .halt_reg = 0x1038,
618 .enable_reg = 0x1038,
619 .enable_mask = BIT(0),
633 .halt_reg = 0x1014,
636 .enable_reg = 0x1014,
637 .enable_mask = BIT(0),
651 .halt_reg = 0x1024,
654 .enable_reg = 0x1024,
655 .enable_mask = BIT(0),
669 .halt_reg = 0x2004,
672 .enable_reg = 0x2004,
673 .enable_mask = BIT(0),
687 .halt_reg = 0x1010,
690 .enable_reg = 0x1010,
691 .enable_mask = BIT(0),
705 .halt_reg = 0x101c,
708 .enable_reg = 0x101c,
709 .enable_mask = BIT(0),
723 .halt_reg = 0x200c,
726 .enable_reg = 0x200c,
727 .enable_mask = BIT(0),
741 .halt_reg = 0x2008,
744 .enable_reg = 0x2008,
745 .enable_mask = BIT(0),
759 .halt_reg = 0x102c,
762 .enable_reg = 0x102c,
763 .enable_mask = BIT(0),
777 .halt_reg = 0x5004,
780 .enable_reg = 0x5004,
781 .enable_mask = BIT(0),
790 .gdscr = 0x1004,
791 .en_rest_wait_val = 0x2,
792 .en_few_wait_val = 0x2,
793 .clk_dis_wait_val = 0xf,
854 .max_register = 0x10000,
883 qcom_branch_set_clk_en(regmap, 0x5008); /* DISP_CC_XO_CLK */