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/linux/drivers/clk/pistachio/
H A Dclk-pistachio.c19 GATE(CLK_MIPS, "mips", "mips_div", 0x104, 0),
20 GATE(CLK_AUDIO_IN, "audio_in", "audio_clk_in_gate", 0x104, 1),
21 GATE(CLK_AUDIO, "audio", "audio_div", 0x104, 2),
22 GATE(CLK_I2S, "i2s", "i2s_div", 0x104, 3),
23 GATE(CLK_SPDIF, "spdif", "spdif_div", 0x104, 4),
24 GATE(CLK_AUDIO_DAC, "audio_dac", "audio_dac_div", 0x104, 5),
25 GATE(CLK_RPU_V, "rpu_v", "rpu_v_div", 0x104, 6),
26 GATE(CLK_RPU_L, "rpu_l", "rpu_l_div", 0x104, 7),
27 GATE(CLK_RPU_SLEEP, "rpu_sleep", "rpu_sleep_div", 0x104, 8),
28 GATE(CLK_WIFI_PLL_GATE, "wifi_pll_gate", "wifi_pll_mux", 0x104, 9),
[all …]
/linux/drivers/memory/tegra/
H A Dtegra20.c18 #define MC_STAT_CONTROL 0x90
19 #define MC_STAT_EMC_CLOCK_LIMIT 0xa0
20 #define MC_STAT_EMC_CLOCKS 0xa4
21 #define MC_STAT_EMC_CONTROL_0 0xa8
22 #define MC_STAT_EMC_CONTROL_1 0xac
23 #define MC_STAT_EMC_COUNT_0 0xb8
24 #define MC_STAT_EMC_COUNT_1 0xbc
32 #define MC_STAT_CONTROL_PRI_EVENT_HP 0
36 #define MC_STAT_CONTROL_FILTER_PRI_DISABLE 0
40 #define MC_STAT_CONTROL_EVENT_QUALIFIED 0
[all …]
/linux/drivers/clk/axs10x/
H A Di2s_pll_clock.c19 #define PLL_IDIV_REG 0x0
20 #define PLL_FBDIV_REG 0x4
21 #define PLL_ODIV0_REG 0x8
22 #define PLL_ODIV1_REG 0xC
34 { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
35 { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
36 { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
37 { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
38 { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
39 { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
[all …]
/linux/include/soc/spacemit/
H A Dk1-syscon.h21 #define APBS_PLL1_SWCR1 0x100
22 #define APBS_PLL1_SWCR2 0x104
23 #define APBS_PLL1_SWCR3 0x108
24 #define APBS_PLL2_SWCR1 0x118
25 #define APBS_PLL2_SWCR2 0x11c
26 #define APBS_PLL2_SWCR3 0x120
27 #define APBS_PLL3_SWCR1 0x124
28 #define APBS_PLL3_SWCR2 0x128
29 #define APBS_PLL3_SWCR3 0x12c
32 #define MPMU_POSR 0x0010
[all …]
/linux/drivers/media/pci/bt8xx/
H A Dbt878.h22 #define BT878_VERSION_CODE 0x000000
24 #define BT878_AINT_STAT 0x100
25 #define BT878_ARISCS (0xf<<28)
38 #define BT878_AINT_MASK 0x104
40 #define BT878_AGPIO_DMA_CTL 0x10c
41 #define BT878_A_GAIN (0xf<<28)
48 #define BT878_DA_LRD (0x1f<<16)
53 #define BT878_DA_SDR (0xf<<8)
61 #define BT878_APACK_LEN 0x110
62 #define BT878_AFP_LEN (0xff<<16)
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-ln-shrd-v6.h9 #define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
10 #define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
11 #define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
12 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
13 #define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
14 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
15 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
16 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
17 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
18 #define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
H A Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_EN_CENTER 0x010
12 #define QSERDES_PLL_SSC_ADJ_PER1 0x014
13 #define QSERDES_PLL_SSC_ADJ_PER2 0x018
14 #define QSERDES_PLL_SSC_PER1 0x01c
15 #define QSERDES_PLL_SSC_PER2 0x020
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
18 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
19 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
[all …]
/linux/drivers/gpu/drm/arm/display/komeda/d71/
H A Dd71_regs.h11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_MAX_LINE_SIZE 0x008
14 #define BLK_VALID_INPUT_ID0 0x020
15 #define BLK_OUTPUT_ID0 0x060
16 #define BLK_INPUT_ID0 0x080
17 #define BLK_IRQ_RAW_STATUS 0x0A0
18 #define BLK_IRQ_CLEAR 0x0A4
19 #define BLK_IRQ_MASK 0x0A8
20 #define BLK_IRQ_STATUS 0x0AC
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c107 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
108 0, 2, 7, 0x1c0, 0),
109 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
110 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
111 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
112 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
114 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
116 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
117 0x018, 0, 1, 7, 0x1C0, 4),
[all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A Duncore-interconnect.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x01",
12 "Counter": "0,1,2,3",
13 "EventCode": "0x16",
16 "UMask": "0x1",
21 "Counter": "0,1,2,3",
22 "EventCode": "0x18",
25 "UMask": "0x1",
30 "Counter": "0,1,2,3",
31 "EventCode": "0x24",
[all …]
/linux/arch/arm/boot/dts/calxeda/
H A Decx-common.dtsi14 cpu_suspend = <0x84000002>;
15 cpu_off = <0x84000004>;
16 cpu_on = <0x84000006>;
27 reg = <0xffe08000 0x10000>;
28 interrupts = <0 83 4>;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
35 calxeda,led-order = <4 0 1 2 3>;
40 reg = <0xffe0e000 0x1000>;
41 interrupts = <0 90 4>;
48 reg = <0xfff20000 0x1000>;
[all …]
/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
14 #define RSTOUTn_MASK_PHYS (ORION5X_BRIDGE_PHYS_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
22 #define BRIDGE_INT_TIMER1_CLR (~0x0004)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-sys-s3c64xx.h16 #define S3C64XX_AHB_CON0 S3C_SYSREG(0x100)
17 #define S3C64XX_AHB_CON1 S3C_SYSREG(0x104)
18 #define S3C64XX_AHB_CON2 S3C_SYSREG(0x108)
20 #define S3C64XX_SDMA_SEL S3C_SYSREG(0x110)
22 #define S3C64XX_OTHERS S3C_SYSREG(0x900)
/linux/Documentation/devicetree/bindings/phy/
H A Dmarvell,berlin2-usb-phy.yaml22 const: 0
39 reg = <0xf774000 0x128>;
40 #phy-cells = <0>;
41 resets = <&chip 0x104 14>;
/linux/drivers/media/rc/keymaps/
H A Drc-minix-neo.c14 { 0x118, KEY_POWER },
16 { 0x146, KEY_UP },
17 { 0x116, KEY_DOWN },
18 { 0x147, KEY_LEFT },
19 { 0x115, KEY_RIGHT },
20 { 0x155, KEY_ENTER },
22 { 0x110, KEY_VOLUMEDOWN },
23 { 0x140, KEY_BACK },
24 { 0x114, KEY_VOLUMEUP },
26 { 0x10d, KEY_HOME },
[all …]
/linux/include/linux/
H A Datmel_pdc.h15 #define ATMEL_PDC_RPR 0x100 /* Receive Pointer Register */
16 #define ATMEL_PDC_RCR 0x104 /* Receive Counter Register */
17 #define ATMEL_PDC_TPR 0x108 /* Transmit Pointer Register */
18 #define ATMEL_PDC_TCR 0x10c /* Transmit Counter Register */
19 #define ATMEL_PDC_RNPR 0x110 /* Receive Next Pointer Register */
20 #define ATMEL_PDC_RNCR 0x114 /* Receive Next Counter Register */
21 #define ATMEL_PDC_TNPR 0x118 /* Transmit Next Pointer Register */
22 #define ATMEL_PDC_TNCR 0x11c /* Transmit Next Counter Register */
24 #define ATMEL_PDC_PTCR 0x120 /* Transfer Control Register */
25 #define ATMEL_PDC_RXTEN (1 << 0) /* Receiver Transfer Enable */
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
/linux/drivers/media/usb/gspca/
H A Dstk1135.h8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_mdio_bf3.h21 #define MLXBF3_GIGE_MDIO_GW_OFFSET 0x80
22 #define MLXBF3_GIGE_MDIO_DATA_READ 0x8c
23 #define MLXBF3_GIGE_MDIO_CFG_REG0 0x100
24 #define MLXBF3_GIGE_MDIO_CFG_REG1 0x104
25 #define MLXBF3_GIGE_MDIO_CFG_REG2 0x108
36 #define MLXBF3_GIGE_MDIO_GW_DATA_READ_MASK GENMASK(15, 0)
45 #define MLXBF3_GIGE_MDIO_GW_DATA_READ_SHIFT 0
48 #define MLXBF3_GIGE_MDIO_CFG_MDIO_MODE_MASK GENMASK(1, 0)
50 #define MLXBF3_GIGE_MDIO_CFG_MDC_PERIOD_MASK GENMASK(7, 0)
51 #define MLXBF3_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK GENMASK(7, 0)
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]

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