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/freebsd/contrib/bearssl/src/symcipher/
H A Ddes_tab.c30 * order (rightmost bit is 0).
36 4, 14, 18, 8, 17, 0, 19
46 24, 7, 13, 0, 21, 17, 1
53 0x00808200, 0x00000000, 0x00008000, 0x00808202,
54 0x00808002, 0x00008202, 0x00000002, 0x00008000,
55 0x00000200, 0x00808200, 0x00808202, 0x00000200,
56 0x00800202, 0x00808002, 0x00800000, 0x00000002,
57 0x00000202, 0x00800200, 0x00800200, 0x00008200,
58 0x00008200, 0x00808000, 0x00808000, 0x00800202,
59 0x00008002, 0x00800002, 0x00800002, 0x00008002,
[all …]
/freebsd/crypto/krb5/src/lib/crypto/builtin/des/
H A Df_tables.c65 * ((left & 0x55555555) << 1) | (right & 0x55555555) for left half
66 * (left & 0xaaaaaaaa) | ((right & 0xaaaaaaaa) >> 1) for right half
76 0x00000000, 0x00000010, 0x00000001, 0x00000011,
77 0x00001000, 0x00001010, 0x00001001, 0x00001011,
78 0x00000100, 0x00000110, 0x00000101, 0x00000111,
79 0x00001100, 0x00001110, 0x00001101, 0x00001111,
80 0x00100000, 0x00100010, 0x00100001, 0x00100011,
81 0x00101000, 0x00101010, 0x00101001, 0x00101011,
82 0x00100100, 0x00100110, 0x00100101, 0x00100111,
83 0x00101100, 0x00101110, 0x00101101, 0x00101111,
[all …]
/freebsd/sys/contrib/device-tree/src/mips/xilfpga/
H A Dnexys4ddr.dts19 reg = <0x0 0x08000000>;
23 #address-cells = <0>;
33 reg = <0x10200000 0x10000>;
34 xlnx,kind-of-intr = <0x0>;
35 xlnx,num-intr-inputs = <0x6>;
45 reg = <0x10600000 0x10000>;
46 xlnx,all-inputs = <0x0>;
47 xlnx,dout-default = <0x0>;
48 xlnx,gpio-width = <0x16>;
49 xlnx,interrupt-present = <0x0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5260.dtsi35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
128 reg = <0x10200000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Darm-realview-pb1176.dts45 /* 128 MiB memory @ 0x0 */
46 reg = <0x00000000 0x08000000>;
67 #clock-cells = <0>;
73 #clock-cells = <0>;
82 #clock-cells = <0>;
84 clock-frequency = <0>;
89 reg = <0x30000000 0x4000000>;
98 reg = <0x38000000 0x800000>;
113 reg = <0x3c000000 0x4000000>;
121 reg = <0x3a000000 0x10000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3036.dtsi37 #size-cells = <0>;
43 reg = <0xf00>;
56 reg = <0xf01>;
87 #clock-cells = <0>;
92 reg = <0x10080000 0x2000>;
95 ranges = <0 0x10080000 0x2000>;
97 smp-sram@0 {
99 reg = <0x00 0x10>;
105 reg = <0x10090000 0x10000>;
125 reg = <0x10108000 0x800>;
[all …]
H A Drk3128.dtsi44 #size-cells = <0>;
50 reg = <0xf00>;
61 reg = <0xf01>;
69 reg = <0xf02>;
77 reg = <0xf03>;
83 cpu_opp_table: opp-table-0 {
159 #clock-cells = <0>;
164 reg = <0x10080000 0x2000>;
167 ranges = <0 0x10080000 0x2000>;
169 smp-sram@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8365.dtsi24 #size-cells = <0>;
26 cluster0_opp: opp-table-0 {
128 cpu0: cpu@0 {
131 reg = <0x0>;
135 i-cache-size = <0x8000>;
138 d-cache-size = <0x8000>;
151 reg = <0x1>;
155 i-cache-size = <0x8000>;
158 d-cache-size = <0x8000>;
171 reg = <0x2>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dipq8074.dtsi21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #size-cells = <0>;
35 CPU0: cpu@0 {
38 reg = <0x0>;
47 reg = <0x1>;
55 reg = <0x2>;
63 reg = <0x3>;
90 reg = <0x0 0x4a600000 0x0 0x400000>;
95 reg = <0x0 0x4aa00000 0x0 0x100000>;
[all …]
/freebsd/sys/dev/sfxge/common/
H A Def10_tlv_layout.h59 * special values defined in the document, they are of the form 0xLTTTNNNN,
63 * 0: static configuration
100 #define TLV_TAG_END (0xEEEEEEEE)
105 #define TLV_TAG_SKIP (0x00000000)
106 #define TLV_TAG_INVALID (0xFFFFFFFF)
111 * 0.
114 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)
120 /* 0 indicates the default segment (always located at offset 0), while other values
122 * The default segment may also have preset > 0, which means that it is a preset
123 * selected through an RFID command and copied by FW to the location at offset 0. */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/tesla/
H A Dfsd.dtsi39 #size-cells = <0>;
88 /* Cluster 0 */
89 cpucl0_0: cpu@0 {
92 reg = <0x0 0x000>;
96 i-cache-size = <0xc000>;
99 d-cache-size = <0x8000>;
108 reg = <0x0 0x001>;
112 i-cache-size = <0xc000>;
115 d-cache-size = <0x8000>;
124 reg = <0x0 0x002>;
[all …]
/freebsd/sys/contrib/device-tree/src/riscv/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynosautov9.dtsi47 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0>;
91 reg = <0x100>;
98 reg = <0x200>;
105 reg = <0x300>;
112 reg = <0x10000>;
119 reg = <0x10100>;
126 reg = <0x10200>;
133 reg = <0x10300>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dmcp_public.h51 #define OFFSIZE_OFFSET_OFFSET 0
52 #define OFFSIZE_OFFSET_MASK 0x0000ffff
55 #define OFFSIZE_SIZE_MASK 0xffff0000
70 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
71 #define ETH_SPEED_AUTONEG 0
72 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */
75 #define ETH_PAUSE_NONE 0x0
76 #define ETH_PAUSE_AUTONEG 0x1
77 #define ETH_PAUSE_RX 0x2
78 #define ETH_PAUSE_TX 0x4
[all …]
/freebsd/sys/dev/bxe/
H A Decore_hsi.h33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
61 #define PIN_CFG_NA 0x00000000
62 #define PIN_CFG_GPIO0_P0 0x00000001
63 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]