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/linux/include/linux/mtd/
H A Ddoc2000.h17 #define DoC_Sig1 0
20 #define DoC_ChipID 0x1000
21 #define DoC_DOCStatus 0x1001
22 #define DoC_DOCControl 0x1002
23 #define DoC_FloorSelect 0x1003
24 #define DoC_CDSNControl 0x1004
25 #define DoC_CDSNDeviceSelect 0x1005
26 #define DoC_ECCConf 0x1006
27 #define DoC_2k_ECCStatus 0x1007
29 #define DoC_CDSNSlowIO 0x100d
[all …]
/linux/Documentation/devicetree/bindings/soc/sprd/
H A Dsprd,sc9863a-glbregs.yaml33 "@[0-9a-f]+$":
43 reg = <0x20e00000 0x4000>;
44 ranges = <0 0x20e00000 0x4000>;
48 apahb_gate: apahb-gate@0 {
50 reg = <0x0 0x1020>;
/linux/drivers/media/dvb-frontends/
H A Datbm8830_priv.h19 #define REG_CHIP_ID 0x0000
20 #define REG_TUNER_BASEBAND 0x0001
21 #define REG_DEMOD_RUN 0x0004
22 #define REG_DSP_RESET 0x0005
23 #define REG_RAM_RESET 0x0006
24 #define REG_ADC_RESET 0x0007
25 #define REG_TSPORT_RESET 0x0008
26 #define REG_BLKERR_POL 0x000C
27 #define REG_I2C_GATE 0x0103
28 #define REG_TS_SAMPLE_EDGE 0x0301
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-pci-dwc-mshc.c15 #define SDHCI_VENDOR_PTR_R 0xE8
18 #define SDHC_GPIO_OUT 0x34
19 #define SDHC_AT_CTRL_R 0x40
20 #define SDHC_SW_TUNE_EN 0x00000010
23 #define SDHC_MMCM_DIV_REG 0x1020
24 #define DIV_REG_100_MHZ 0x1145
25 #define DIV_REG_200_MHZ 0x1083
26 #define SDHC_MMCM_CLKFBOUT 0x1024
27 #define CLKFBOUT_100_MHZ 0x0000
28 #define CLKFBOUT_200_MHZ 0x0080
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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_spmu_regs.h23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dsprd,sc9863a-clk.yaml81 reg = <0x21500000 0x1000>;
90 reg = <0x20e00000 0x4000>;
93 ranges = <0 0x20e00000 0x4000>;
95 apahb_gate: apahb-gate@0 {
97 reg = <0x0 0x1020>;
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
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/linux/drivers/soc/renesas/
H A Dr9a09g047-sys.c17 #define SYS_LSI_MODE 0x300
19 * BOOTPLLCA[1:0]
20 * [0,0] => 1.1GHZ
21 * [0,1] => 1.5GHZ
22 * [1,0] => 1.6GHZ
26 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
28 #define SYS_LSI_PRR 0x308
32 #define SYS_LSI_OTPTSU1TRMVAL0 0x330
33 #define SYS_LSI_OTPTSU1TRMVAL1 0x334
34 #define SYS_SPI_STAADDCS0 0x900
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H A Dr9a09g057-sys.c17 #define SYS_LSI_MODE 0x300
19 * BOOTPLLCA[1:0]
20 * [0,0] => 1.1GHZ
21 * [0,1] => 1.5GHZ
22 * [1,0] => 1.6GHZ
26 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
28 #define SYS_LSI_PRR 0x308
29 #define SYS_LSI_PRR_GPU_DIS BIT(0)
32 #define SYS_LSI_OTPTSU0TRMVAL0 0x320
33 #define SYS_LSI_OTPTSU0TRMVAL1 0x324
[all …]
H A Dr9a09g056-sys.c17 #define SYS_LSI_MODE 0x300
20 * BOOTPLLCA[1:0]
21 * [0,0] => 1.1GHZ
22 * [0,1] => 1.5GHZ
23 * [1,0] => 1.6GHZ
27 #define SYS_LSI_MODE_CA55_1_7GHZ 0x3
29 #define SYS_LSI_PRR 0x308
30 #define SYS_LSI_PRR_GPU_DIS BIT(0)
33 #define SYS_RZV2N_FEATURE_G31 BIT(0)
37 #define SYS_LSI_OTPTSU0TRMVAL0 0x320
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/linux/include/sound/
H A Dcs48l32_registers.h13 #define CS48L32_DEVID 0x0
14 #define CS48L32_REVID 0x4
15 #define CS48L32_OTPID 0x10
16 #define CS48L32_SFT_RESET 0x20
17 #define CS48L32_CTRL_IF_DEBUG3 0xA8
18 #define CS48L32_MCU_CTRL1 0x804
19 #define CS48L32_GPIO1_CTRL1 0xc08
20 #define CS48L32_GPIO3_CTRL1 0xc10
21 #define CS48L32_GPIO7_CTRL1 0xc20
22 #define CS48L32_GPIO16_CTRL1 0xc44
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/linux/drivers/net/ethernet/marvell/octeontx2/af/cn20k/
H A Dreg.h14 #define RVU_PF_DISC (0x0)
15 #define RVU_PRIV_PFX_DISC(a) (0x8000208 | (a) << 16)
16 #define RVU_PRIV_HWVFX_DISC(a) (0xD000000 | (a) << 12)
20 #define RVU_MBOX_AF_PFX_ADDR(a) (0x5000 | (a) << 4)
21 #define RVU_MBOX_AF_PFX_CFG(a) (0x6000 | (a) << 4)
22 #define RVU_MBOX_AF_AFPFX_TRIGX(a) (0x9000 | (a) << 3)
23 #define RVU_MBOX_AF_PFAF_INT(a) (0x2980 | (a) << 6)
24 #define RVU_MBOX_AF_PFAF_INT_W1S(a) (0x2988 | (a) << 6)
25 #define RVU_MBOX_AF_PFAF_INT_ENA_W1S(a) (0x2990 | (a) << 6)
26 #define RVU_MBOX_AF_PFAF_INT_ENA_W1C(a) (0x2998 | (a) << 6)
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/linux/arch/sh/include/mach-common/mach/
H A Durquell.h6 * ------ 0x00000000 ------------------------------------
8 * -----+ 0x04000000 ------------------------------------
10 * -----+ 0x08000000 ------------------------------------
13 * -----+ 0x10000000 ------------------------------------
15 * -----+ 0x14000000 ------------------------------------
17 * -----+ 0x18000000 ------------------------------------
19 * -----+ 0x1c000000 ------------------------------------
24 #define NOR_FLASH_ADDR 0x00000000
25 #define NOR_FLASH_SIZE 0x04000000
27 #define CS1_BASE 0x05000000
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/linux/drivers/gpu/drm/hisilicon/kirin/
H A Dkirin_ade_reg.h15 #define ADE_CTRL 0x0004
16 #define FRM_END_START_OFST 0
18 #define AUTO_CLK_GATE_EN_OFST 0
19 #define AUTO_CLK_GATE_EN BIT(0)
20 #define ADE_DISP_SRC_CFG 0x0018
21 #define ADE_CTRL1 0x008C
22 #define ADE_EN 0x0100
23 #define ADE_DISABLE 0
26 #define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
27 #define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
[all …]
/linux/drivers/gpu/drm/lima/
H A Dlima_regs.h14 #define LIMA_PMU_POWER_UP 0x00
15 #define LIMA_PMU_POWER_DOWN 0x04
16 #define LIMA_PMU_POWER_GP0_MASK BIT(0)
29 #define LIMA_PMU_STATUS 0x08
30 #define LIMA_PMU_INT_MASK 0x0C
31 #define LIMA_PMU_INT_RAWSTAT 0x10
32 #define LIMA_PMU_INT_CLEAR 0x18
33 #define LIMA_PMU_INT_CMD_MASK BIT(0)
34 #define LIMA_PMU_SW_DELAY 0x1C
37 #define LIMA_L2_CACHE_SIZE 0x0004
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/linux/drivers/phy/samsung/
H A Dphy-exynos-pcie.c18 #define PCIE_PHY_OFFSET(x) ((x) * 0x4)
21 #define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
22 #define PCIE_MAC_RESET_MASK 0xFF
24 #define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
25 #define PCIE_REFCLK_GATING_EN BIT(0)
26 #define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
27 #define PCIE_PHY_RESET BIT(0)
28 #define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
29 #define PCIE_GLOBAL_RESET BIT(0)
31 #define PCIE_REFCLK_MASK 0x16
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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi22 reg = <0 0x20e00000 0 0x4000>;
25 ranges = <0 0 0x20e00000 0x4000>;
27 apahb_gate: apahb-gate@0 {
29 reg = <0x0 0x1020>;
37 reg = <0 0x402b0000 0 0x4000>;
40 ranges = <0 0 0x402b0000 0x4000>;
42 pmu_gate: pmu-gate@0 {
44 reg = <0 0x1200>;
54 reg = <0 0x402e0000 0 0x4000>;
57 ranges = <0 0 0x402e0000 0x4000>;
[all …]
/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson_regs.h25 "parse_r __res,%0\n\t" in read_cpucfg()
29 ".word (0xc8080118 | (reg << 21) | (__res << 11))\n\t" in read_cpucfg()
38 #define LOONGSON_CFG0 0x0
39 #define LOONGSON_CFG0_PRID GENMASK(31, 0)
41 #define LOONGSON_CFG1 0x1
42 #define LOONGSON_CFG1_FP BIT(0)
74 #define LOONGSON_CFG2 0x2
75 #define LOONGSON_CFG2_LEXT1 BIT(0)
104 #define LOONGSON_CFG3 0x3
105 #define LOONGSON_CFG3_LCAMP BIT(0)
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23-pinfunc.h13 #define MX23_PAD_GPMI_D00__GPMI_D00 0x0000
14 #define MX23_PAD_GPMI_D01__GPMI_D01 0x0010
15 #define MX23_PAD_GPMI_D02__GPMI_D02 0x0020
16 #define MX23_PAD_GPMI_D03__GPMI_D03 0x0030
17 #define MX23_PAD_GPMI_D04__GPMI_D04 0x0040
18 #define MX23_PAD_GPMI_D05__GPMI_D05 0x0050
19 #define MX23_PAD_GPMI_D06__GPMI_D06 0x0060
20 #define MX23_PAD_GPMI_D07__GPMI_D07 0x0070
21 #define MX23_PAD_GPMI_D08__GPMI_D08 0x0080
22 #define MX23_PAD_GPMI_D09__GPMI_D09 0x0090
[all …]
/linux/arch/m68k/include/asm/
H A Dmac_psc.h37 #define PSC_BASE (0x50F31000)
44 * To access a particular set of registers, add 0xn0 to the base
48 #define pIFRbase 0x100
49 #define pIERbase 0x104
55 #define PSC_MYSTERY 0x804
57 #define PSC_CTL_BASE 0xC00
59 #define PSC_SCSI_CTL 0xC00
60 #define PSC_ENETRD_CTL 0xC10
61 #define PSC_ENETWR_CTL 0xC20
62 #define PSC_FDC_CTL 0xC30
[all …]
/linux/drivers/clk/qcom/
H A Ddispcc-sm6350.c36 { 249600000, 2000000000, 0 },
40 .l = 0x3a,
41 .alpha = 0x5555,
42 .config_ctl_val = 0x20485699,
43 .config_ctl_hi_val = 0x00002067,
44 .test_ctl_val = 0x40000000,
45 .test_ctl_hi_val = 0x00000002,
46 .user_ctl_val = 0x00000000,
47 .user_ctl_hi_val = 0x00004805,
51 .offset = 0x0,
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/nic/
H A Dotx2_reg.h14 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
15 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
16 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
17 #define RVU_PF_VF_BAR4_ADDR (0x10)
18 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
19 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
20 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
21 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
22 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
23 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-ccimx6ulsbcpro.dts21 pwms = <&pwm5 0 50000 0>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
51 pinctrl-0 = <&pinctrl_adc1>;
57 pinctrl-0 = <&pinctrl_flexcan1>;
65 pinctrl-0 = <&pinctrl_flexcan2>;
73 pinctrl-0 = <&pinctrl_ecspi1_master>;
79 pinctrl-0 = <&pinctrl_enet1>;
87 pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
96 #size-cells = <0>;
98 ethphy0: ethernet-phy@0 {
[all …]

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