Searched +full:0 +full:x10120000 (Results 1 – 10 of 10) sorted by relevance
8 - #phy-cells: should be 017 reg = <0x10120000 0x1000>;18 #phy-cells = <0>;
19 reg = <0x10140000 0x1000>;27 reg = <0x10003000 0x28>;35 reg = <0x101f1000 0x1000>;44 reg = <0x101f2000 0x1000>;53 reg = <0x101f3000 0x1000>;62 reg = <0x101e2000 0x40>;70 reg = <0x10000044 0x471 0x10001000 0x100072 0x41000000 0x0100000073 0x42000000 0x02000000>;[all …]
10 #size-cells = <0>;12 cpu@0 {15 reg = <0>;25 #address-cells = <0>;33 reg = <0x10000000 0x200000>;34 ranges = <0x0 0x10000000 0x1FFFFF>;39 sysc: system-controller@0 {41 reg = <0x0 0x60>;46 reg = <0x60 0x8>;48 #size-cells = <0>;[all …]
24 reg = <0x0 0x08000000>;28 #clock-cells = <0>;38 #size-cells = <0>;40 port@0 {41 reg = <0>;71 reg = <0x10000000 0x200>;72 ranges = <0x0 0x10000000 0x200>;76 led@8,0 {78 reg = <0x08 0x04>;79 offset = <0x08>;[all …]
45 /* 128 MiB memory @ 0x0 */46 reg = <0x00000000 0x08000000>;67 #clock-cells = <0>;73 #clock-cells = <0>;82 #clock-cells = <0>;84 clock-frequency = <0>;89 reg = <0x30000000 0x4000000>;98 reg = <0x38000000 0x800000>;113 reg = <0x3c000000 0x4000000>;121 reg = <0x3a000000 0x10000>;[all …]
14 reg = <0x00000000 0x04000000>,15 <0x08000000 0x04000000>;20 reg = <0x10210000 0x1000>;37 reg = <0x101e2000 0x1000>;46 reg = <0x101e3000 0x100[all...]
59 * special values defined in the document, they are of the form 0xLTTTNNNN,63 * 0: static configuration100 #define TLV_TAG_END (0xEEEEEEEE)105 #define TLV_TAG_SKIP (0x00000000)106 #define TLV_TAG_INVALID (0xFFFFFFFF)111 * 0.114 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)120 /* 0 indicates the default segment (always located at offset 0), while other values122 * The default segment may also have preset > 0, which means that it is a preset123 * selected through an RFID command and copied by FW to the location at offset 0. */[all …]
51 #define OFFSIZE_OFFSET_OFFSET 052 #define OFFSIZE_OFFSET_MASK 0x0000ffff55 #define OFFSIZE_SIZE_MASK 0xffff000070 u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */71 #define ETH_SPEED_AUTONEG 072 #define ETH_SPEED_SMARTLINQ 0x8 /* deprecated - use link_modes field instead */75 #define ETH_PAUSE_NONE 0x076 #define ETH_PAUSE_AUTONEG 0x177 #define ETH_PAUSE_RX 0x278 #define ETH_PAUSE_TX 0x4[all …]
33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 041 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF000047 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 049 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF000061 #define PIN_CFG_NA 0x0000000062 #define PIN_CFG_GPIO0_P0 0x0000000163 #define PIN_CFG_GPIO1_P0 0x00000002[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]