| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | rpm.h | 14 #define PCI_DEVID_CN10K_RPM 0xA060 15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00 16 #define PCI_DEVID_CN10KB_RPM 0xA09F 19 #define RPMX_CMRX_CFG 0x00 20 #define RPMX_CMR_GLOBAL_CFG 0x08 24 #define RPMX_CMRX_RX_ID_MAP 0x80 25 #define RPMX_CMRX_SW_INT 0x180 26 #define RPMX_CMRX_SW_INT_W1S 0x188 27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198 28 #define RPMX_CMRX_LINK_CFG 0x1070 [all …]
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | raspberrypi,rp1-clocks.yaml | 54 reg = <0xc0 0x40018000 0x0 0x10038>;
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | pci1de4,1.yaml | 36 - IO BANK0: 0 67 - USB HOST0-0: 31 72 - USB HOST1-0: 36 114 rp1@0,0 { 116 ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>; 124 ranges = <0x00 0x40000000 0x01 0x00 0x00000000 0x00 0x00400000>; 125 dma-ranges = <0x10 0x00000000 0x43000000 0x10 0x00000000 0x10 0x00000000>; 131 reg = <0x00 0x40018000 0x0 0x10038>;
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| /linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
| H A D | bif_3_0_d.h | 26 #define ixPB0_DFT_DEBUG_CTRL_REG0 0x1300C 27 #define ixPB0_DFT_JIT_INJ_REG0 0x13000 28 #define ixPB0_DFT_JIT_INJ_REG1 0x13004 29 #define ixPB0_DFT_JIT_INJ_REG2 0x13008 30 #define ixPB0_GLB_CTRL_REG0 0x10004 31 #define ixPB0_GLB_CTRL_REG1 0x10008 32 #define ixPB0_GLB_CTRL_REG2 0x1000C 33 #define ixPB0_GLB_CTRL_REG3 0x10010 34 #define ixPB0_GLB_CTRL_REG4 0x10014 35 #define ixPB0_GLB_CTRL_REG5 0x10018 [all …]
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| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | pipeline.json | 3 "EventCode": "0x10004", 8 "EventCode": "0x10006", 13 "EventCode": "0x1000C", 18 "EventCode": "0x1000E", 23 "EventCode": "0x10012", 28 "EventCode": "0x10014", 33 "EventCode": "0x10018", 38 "EventCode": "0x10028", 43 "EventCode": "0x10038", 48 "EventCode": "0x1003A", [all …]
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| /linux/arch/powerpc/perf/ |
| H A D | power7-events-list.h | 8 EVENT(PM_IC_DEMAND_L2_BR_ALL, 0x04898) 9 EVENT(PM_GCT_UTIL_7_TO_10_SLOTS, 0x020a0) 10 EVENT(PM_PMC2_SAVED, 0x10022) 11 EVENT(PM_CMPLU_STALL_DFU, 0x2003c) 12 EVENT(PM_VSU0_16FLOP, 0x0a0a4) 13 EVENT(PM_MRK_LSU_DERAT_MISS, 0x3d05a) 14 EVENT(PM_MRK_ST_CMPL, 0x10034) 15 EVENT(PM_NEST_PAIR3_ADD, 0x40881) 16 EVENT(PM_L2_ST_DISP, 0x46180) 17 EVENT(PM_L2_CASTOUT_MOD, 0x16180) [all …]
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| /linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx6qdl-zii-rdu2.dtsi | 22 #size-cells = <0>; 24 pinctrl-0 = <&pinctrl_mdio1>; 28 phy: ethernet-phy@0 { 29 pinctrl-0 = <&pinctrl_rmii_phy_irq>; 31 reg = <0>; 84 pinctrl-0 = <&pinctrl_reg_3p3v_sd>; 177 #size-cells = <0>; 180 pinctrl-0 = <&pinctrl_disp0>; 183 port@0 { 184 reg = <0>; [all …]
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| /linux/drivers/mtd/nand/raw/ |
| H A D | lpc32xx_mlc.c | 41 #define MLC_BUFF(x) (x + 0x00000) 42 #define MLC_DATA(x) (x + 0x08000) 43 #define MLC_CMD(x) (x + 0x10000) 44 #define MLC_ADDR(x) (x + 0x10004) 45 #define MLC_ECC_ENC_REG(x) (x + 0x10008) 46 #define MLC_ECC_DEC_REG(x) (x + 0x1000C) 47 #define MLC_ECC_AUTO_ENC_REG(x) (x + 0x10010) 48 #define MLC_ECC_AUTO_DEC_REG(x) (x + 0x10014) 49 #define MLC_RPR(x) (x + 0x10018) 50 #define MLC_WPR(x) (x + 0x1001C) [all …]
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| /linux/drivers/pinctrl/tegra/ |
| H A D | pinctrl-tegra234.c | 1433 .mux_bit = 0, \ 1447 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1448 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1449 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1450 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1451 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1452 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1453 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1454 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1455 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0) [all …]
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| H A D | pinctrl-tegra194.c | 1333 .mux_bit = 0, \ 1348 …efine drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1349 …efine drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1350 …efine drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1351 …efine drive_soc_gpio30_ps5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1352 …efine drive_aud_mclk_ps4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1353 …efine drive_dap1_fs_ps3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1354 …efine drive_dap1_din_ps2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1355 …efine drive_dap1_dout_ps1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0) 1356 …efine drive_dap1_sclk_ps0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0) [all …]
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| /linux/drivers/clk/qcom/ |
| H A D | gcc-sm8250.c | 36 .offset = 0x0, 39 .enable_reg = 0x52018, 40 .enable_mask = BIT(0), 53 { 0x1, 2 }, 58 .offset = 0x0, 75 .offset = 0x76000, 78 .enable_reg = 0x52018, 92 .offset = 0x1c000, 95 .enable_reg = 0x52018, 109 { P_BI_TCXO, 0 }, [all …]
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| H A D | gcc-sm8350.c | 44 .offset = 0x0, 47 .enable_reg = 0x52018, 48 .enable_mask = BIT(0), 61 { 0x1, 2 }, 66 .offset = 0x0, 83 .offset = 0x76000, 86 .enable_reg = 0x52018, 101 .offset = 0x1c000, 104 .enable_reg = 0x52018, 119 { P_BI_TCXO, 0 }, [all …]
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| H A D | gcc-sc8280xp.c | 113 .offset = 0x0, 116 .enable_reg = 0x52028, 117 .enable_mask = BIT(0), 128 { 0x1, 2 }, 133 .offset = 0x0, 150 .offset = 0x2000, 153 .enable_reg = 0x52028, 165 .offset = 0x76000, 168 .enable_reg = 0x52028, 180 .offset = 0x1a000, [all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/nbio/ |
| H A D | nbio_7_0_offset.h | 27 // base address: 0x0 28 …NB_NBCFG0_NB_VENDOR_ID 0x0000 29 …NB_NBCFG0_NB_DEVICE_ID 0x0002 30 …NB_NBCFG0_NB_COMMAND 0x0004 31 …NB_NBCFG0_NB_STATUS 0x0006 32 …NB_NBCFG0_NB_REVISION_ID 0x0008 33 …NB_NBCFG0_NB_REGPROG_INF 0x0009 34 …NB_NBCFG0_NB_SUB_CLASS 0x000a 35 …NB_NBCFG0_NB_BASE_CODE 0x000b 36 …NB_NBCFG0_NB_CACHE_LINE 0x000c [all …]
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