41 #define MLC_BUFF(x)			(x + 0x00000)
42 #define MLC_DATA(x)			(x + 0x08000)
43 #define MLC_CMD(x)			(x + 0x10000)
44 #define MLC_ADDR(x)			(x + 0x10004)
45 #define MLC_ECC_ENC_REG(x)		(x + 0x10008)
46 #define MLC_ECC_DEC_REG(x)		(x + 0x1000C)
47 #define MLC_ECC_AUTO_ENC_REG(x)		(x + 0x10010)
48 #define MLC_ECC_AUTO_DEC_REG(x)		(x + 0x10014)
49 #define MLC_RPR(x)			(x + 0x10018)
50 #define MLC_WPR(x)			(x + 0x1001C)
51 #define MLC_RUBP(x)			(x + 0x10020)
52 #define MLC_ROBP(x)			(x + 0x10024)
53 #define MLC_SW_WP_ADD_LOW(x)		(x + 0x10028)
54 #define MLC_SW_WP_ADD_HIG(x)		(x + 0x1002C)
55 #define MLC_ICR(x)			(x + 0x10030)
56 #define MLC_TIME_REG(x)			(x + 0x10034)
57 #define MLC_IRQ_MR(x)			(x + 0x10038)
58 #define MLC_IRQ_SR(x)			(x + 0x1003C)
59 #define MLC_LOCK_PR(x)			(x + 0x10044)
60 #define MLC_ISR(x)			(x + 0x10048)
61 #define MLC_CEH(x)			(x + 0x1004C)
66 #define MLCCMD_RESET			0xFF
74 #define MLCICR_16BIT			(1 << 0)  /* unsupported by LPC32x0! */
79 #define MLCTIMEREG_TCEA_DELAY(n)	(((n) & 0x03) << 24)
80 #define MLCTIMEREG_BUSY_DELAY(n)	(((n) & 0x1F) << 19)
81 #define MLCTIMEREG_NAND_TA(n)		(((n) & 0x07) << 16)
82 #define MLCTIMEREG_RD_HIGH(n)		(((n) & 0x0F) << 12)
83 #define MLCTIMEREG_RD_LOW(n)		(((n) & 0x0F) << 8)
84 #define MLCTIMEREG_WR_HIGH(n)		(((n) & 0x0F) << 4)
85 #define MLCTIMEREG_WR_LOW(n)		(((n) & 0x0F) << 0)
95 #define MLCIRQ_WRPROT_FAULT		(1 << 0)
100 #define MLCLOCKPR_MAGIC			0xA25E
110 #define MLCISR_NAND_READY		(1 << 0)
115 #define MLCCEH_NORMAL			(1 << 0)
140 	return 0;  in lpc32xx_ooblayout_ecc()
154 	return 0;  in lpc32xx_ooblayout_free()
165 	.pages = { 524224, 0, 0, 0, 0, 0, 0, 0 },
171 	.pages = { 524160, 0, 0, 0, 0, 0, 0, 0 },
241 	if (clkrate == 0)  in lpc32xx_nand_setup()
257 	tmp = 0;  in lpc32xx_nand_setup()
303 	return 0;  in lpc32xx_nand_device_ready()
384 		gpiod_set_value_cansleep(host->wp_gpio, 0);  in lpc32xx_wp_disable()
427 	return 0;  in lpc32xx_xmit_dma()
455 	nand_read_page_op(chip, page, 0, NULL, 0);  in lpc32xx_read_page()
458 	for (i = 0; i < host->mlcsubpages; i++) {  in lpc32xx_read_page()
460 		writeb(0x00, MLC_ECC_AUTO_DEC_REG(host->io_base));  in lpc32xx_read_page()
471 			mtd->ecc_stats.corrected += ((mlc_isr >> 4) & 0x3) + 1;  in lpc32xx_read_page()
481 			for (j = 0; j < (512 >> 2); j++) {  in lpc32xx_read_page()
487 		for (j = 0; j < (16 >> 2); j++) {  in lpc32xx_read_page()
497 	return 0;  in lpc32xx_read_page()
516 	nand_prog_page_begin_op(chip, page, 0, NULL, 0);  in lpc32xx_write_page_lowlevel()
518 	for (i = 0; i < host->mlcsubpages; i++) {  in lpc32xx_write_page_lowlevel()
520 		writeb(0x00, MLC_ECC_ENC_REG(host->io_base));  in lpc32xx_write_page_lowlevel()
529 			for (j = 0; j < (512 >> 2); j++) {  in lpc32xx_write_page_lowlevel()
540 		/* Auto Encode w/ Bit 8 = 0 (see LPC MLC Controller manual) */  in lpc32xx_write_page_lowlevel()
541 		writeb(0x00, MLC_ECC_AUTO_ENC_REG(host->io_base));  in lpc32xx_write_page_lowlevel()
557 	return 0;  in lpc32xx_read_oob()
563 	return 0;  in lpc32xx_write_oob()
614 	return 0;  in lpc32xx_dma_setup()
654 		return 0;  in lpc32xx_nand_attach_chip()
678 	return 0;  in lpc32xx_nand_attach_chip()
703 	host->io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &rc);  in lpc32xx_nand_probe()
782 	host->irq = platform_get_irq(pdev, 0);  in lpc32xx_nand_probe()
783 	if (host->irq < 0) {  in lpc32xx_nand_probe()
811 	return 0;  in lpc32xx_nand_probe()
871 	return 0;  in lpc32xx_nand_resume()
883 	return 0;  in lpc32xx_nand_suspend()