| /linux/Documentation/devicetree/bindings/perf/ |
| H A D | riscv,pmu.yaml | 78 value of variant must be 0xffffffff_ffffffff.
104 riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
105 riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
106 <0x00002 0x00002 0x00000004>,
107 <0x00003 0x0000A 0x00000ff8>,
108 <0x10000 0x10033 0x000ff000>;
110 /* For event ID 0x0002 */
111 <0x0000 0x0002 0xffffffff 0xffffffff 0x00000f8>,
112 /* For event ID 0-4 */
113 <0x0 0x0 0xffffffff 0xfffffff0 0x00000ff0>,
[all …]
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| /linux/tools/include/linux/ |
| H A D | arm-smccc.h | 18 #define ARM_SMCCC_STD_CALL _AC(0,U)
22 #define ARM_SMCCC_SMC_32 0
26 #define ARM_SMCCC_OWNER_MASK 0x3F
29 #define ARM_SMCCC_FUNC_MASK 0xFFFF
45 #define ARM_SMCCC_OWNER_ARCH 0
57 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
59 #define ARM_SMCCC_QUIRK_NONE 0
62 #define ARM_SMCCC_VERSION_1_0 0x10000
63 #define ARM_SMCCC_VERSION_1_1 0x10001
64 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
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| /linux/arch/x86/include/asm/shared/ |
| H A D | tdx.h | 8 #define TDX_HYPERCALL_STANDARD 0
10 #define TDX_CPUID_LEAF_ID 0x21
14 #define TDG_VP_VMCALL 0
24 #define TDX_ATTR_DEBUG_BIT 0
50 #define TDCS_CONFIG_FLAGS 0x1110000300000016
51 #define TDCS_TD_CTLS 0x1110000300000017
52 #define TDCS_NOTIFY_ENABLES 0x9100000000000010
53 #define TDCS_TOPOLOGY_ENUM_CONFIGURED 0x9100000000000019
59 #define TD_CTLS_PENDING_VE_DISABLE_BIT 0
71 #define TDVMCALL_GET_TD_VM_CALL_INFO 0x10000
[all …]
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| /linux/Documentation/admin-guide/perf/ |
| H A D | hns3-pmu.rst | 44 config=0x00204
46 config=0x10204
51 The bits 0~15 of config (here 0x0204) are the true hardware event code. If
52 two events have same value of bits 0~15 of config, that means they are
53 event pair. And the bit 16 of config indicates getting counter 0 or
59 counter 0 / counter 1
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
90 is same as mac id. The "tc" filter option must be set to 0xF in this mode,
95 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
[all …]
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| /linux/drivers/media/platform/qcom/venus/ |
| H A D | hfi_cmds.h | 12 #define HFI_CMD_SYS_INIT 0x10001
13 #define HFI_CMD_SYS_PC_PREP 0x10002
14 #define HFI_CMD_SYS_SET_RESOURCE 0x10003
15 #define HFI_CMD_SYS_RELEASE_RESOURCE 0x10004
16 #define HFI_CMD_SYS_SET_PROPERTY 0x10005
17 #define HFI_CMD_SYS_GET_PROPERTY 0x10006
18 #define HFI_CMD_SYS_SESSION_INIT 0x10007
19 #define HFI_CMD_SYS_SESSION_END 0x10008
20 #define HFI_CMD_SYS_SET_BUFFERS 0x10009
21 #define HFI_CMD_SYS_TEST_SSR 0x10101
[all …]
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| /linux/arch/riscv/boot/dts/thead/ |
| H A D | th1520.dtsi | 19 #size-cells = <0>;
22 c910_0: cpu@0 {
32 reg = <0>;
143 <0x00003 0x00003 0x0007fff8>,
144 <0x00004 0x00004 0x0007fff8>,
145 <0x00005 0x00005 0x0007fff8>,
146 <0x00006 0x00006 0x0007fff8>,
147 <0x00007 0x00007 0x0007fff8>,
148 <0x00008 0x00008 0x0007fff8>,
149 <0x00009 0x00009 0x0007fff8>,
[all …]
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| /linux/include/uapi/linux/ |
| H A D | dlmconstants.h | 31 #define DLM_LOCK_NL 0 /* null */
46 * either return -EAGAIN from the dlm_lock call or will return 0 from
140 #define DLM_LKF_NOQUEUE 0x00000001
141 #define DLM_LKF_CANCEL 0x00000002
142 #define DLM_LKF_CONVERT 0x00000004
143 #define DLM_LKF_VALBLK 0x00000008
144 #define DLM_LKF_QUECVT 0x00000010
145 #define DLM_LKF_IVVALBLK 0x00000020
146 #define DLM_LKF_CONVDEADLK 0x00000040
147 #define DLM_LKF_PERSISTENT 0x00000080
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/clearwaterforest/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x2e",
9 "UMask": "0x41"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0x2e",
18 "UMask": "0x4f"
22 "Counter": "0,1,2,3,4,5,6,7",
23 "EventCode": "0xd0",
25 "PublicDescription": "Counts the number of load ops retired. Available PDIST counters: 0,1",
27 "UMask": "0x81"
[all …]
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| /linux/tools/perf/pmu-events/ |
| H A D | empty-pmu-events.c | 22 /* offset=0 */ "default_core\000"
23 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\00…
24 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\00…
25 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\00…
26 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\00…
27 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\00…
28 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00010\000\000\00…
29 …es\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00000\000\…
30 …ss\000legacy cache\000Level 1 data cache read misses\000legacy-cache-config=0x10000\000\00010\000\…
31 …\000legacy cache\000Level 1 data cache read accesses\000legacy-cache-config=0\000\00000\000\000\00…
[all …]
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| /linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/ |
| H A D | sdio.h | 13 #define SDIOD_FBR_SIZE 0x100
16 #define SDIO_FUNC_ENABLE_1 0x02
17 #define SDIO_FUNC_ENABLE_2 0x04
20 #define SDIO_FUNC_READY_1 0x02
21 #define SDIO_FUNC_READY_2 0x04
24 #define INTR_STATUS_FUNC1 0x2
25 #define INTR_STATUS_FUNC2 0x4
28 #define REG_F0_REG_MASK 0x7FF
29 #define REG_F1_MISC_MASK 0x1FFFF
31 /* function 0 vendor specific CCCR registers */
[all …]
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| /linux/Documentation/core-api/ |
| H A D | unaligned-memory-access.rst | 23 from an address that is not evenly divisible by N (i.e. addr % N != 0).
24 For example, reading 4 bytes of data from address 0x10004 is fine, but
25 reading 4 bytes of data from address 0x10005 would be an unaligned memory
41 divisible by N, i.e. addr % N == 0.
94 starting at address 0x10000. With a basic level of understanding, it would
97 structure, i.e. address 0x10002, but that address is not evenly divisible
159 return fold == 0;
163 return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2])) == 0;
169 able to access memory on arbitrary boundaries, the reference to a[0] causes
172 Think about what would happen if addr1 was an odd address such as 0x10003.
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x51",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0x25",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3,4,5,6,7",
23 "EventCode": "0x25",
27 "UMask": "0x10"
31 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/include/linux/ |
| H A D | arm-smccc.h | 25 #define ARM_SMCCC_STD_CALL _AC(0,U)
29 #define ARM_SMCCC_SMC_32 0
33 #define ARM_SMCCC_OWNER_MASK 0x3F
36 #define ARM_SMCCC_FUNC_MASK 0xFFFF
52 #define ARM_SMCCC_OWNER_ARCH 0
64 #define ARM_SMCCC_FUNC_QUERY_CALL_UID 0xff01
66 #define ARM_SMCCC_QUIRK_NONE 0
69 #define ARM_SMCCC_VERSION_1_0 0x10000
70 #define ARM_SMCCC_VERSION_1_1 0x10001
71 #define ARM_SMCCC_VERSION_1_2 0x10002
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x51",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0x25",
18 "UMask": "0x4"
22 "Counter": "0,1,2,3,4,5,6,7",
23 "EventCode": "0x25",
27 "UMask": "0x10"
31 "Counter": "0,1,2,3,4,5,6,7",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/meteorlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x51",
9 "UMask": "0x1",
14 "Counter": "0,1,2,3",
15 "EventCode": "0x51",
18 "UMask": "0x20",
23 "Counter": "0,1,2,3",
24 "EventCode": "0x51",
28 "UMask": "0x1",
33 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/pantherlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7,8,9",
5 "EventCode": "0x51",
9 "UMask": "0x1",
14 "Counter": "0,1,2,3,4,5,6,7,8,9",
15 "EventCode": "0x51",
19 "UMask": "0x4",
24 "Counter": "0,1,2,3,4,5,6,7,8,9",
25 "EventCode": "0x51",
29 "UMask": "0x5",
34 "Counter": "0,1,2,3,4,5,6,7,8,9",
[all …]
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| /linux/drivers/firmware/cirrus/test/ |
| H A D | cs_dsp_test_bin.c | 82 .id = 0xfafa,
83 .ver = 0x100000,
89 .id = 0xfbfb,
90 .ver = 0x100000,
96 .id = 0xc321,
97 .ver = 0x100000,
103 .id = 0xb123,
104 .ver = 0x100000,
148 0); in bin_patch_one_word()
153 reg_val = 0; in bin_patch_one_word()
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
8 "UMask": "0x20",
13 "Counter": "0,1,2,3",
14 "EventCode": "0x51",
18 "UMask": "0x1",
23 "Counter": "0,1,2,3",
24 "EventCode": "0x48",
28 "UMask": "0x2",
33 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/lunarlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5,6,7",
5 "EventCode": "0x31",
13 "Counter": "0,1,2,3,4,5,6,7",
14 "EventCode": "0x51",
18 "UMask": "0x1",
23 "Counter": "0,1,2,3,4,5,6,7,8,9",
24 "EventCode": "0x51",
28 "UMask": "0x1",
33 "Counter": "0,1,2,3,4,5,6,7,8,9",
34 "EventCode": "0x51",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3,4,5",
5 "EventCode": "0x24",
12 "Counter": "0,1,2,3,4,5",
13 "EventCode": "0x24",
17 "UMask": "0x2"
21 "Counter": "0,1,2,3,4,5",
22 "EventCode": "0x24",
26 "UMask": "0x1"
30 "Counter": "0,1,2,3,4,5",
31 "EventCode": "0x2e",
[all …]
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| /linux/drivers/gpu/drm/radeon/ |
| H A D | rv770.c | 56 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks()
71 return 0; in rv770_set_uvd_clocks()
75 43663, 0x03FFFFFE, 1, 30, ~0, in rv770_set_uvd_clocks()
84 /* set UPLL_FB_DIV to 0x50000 */ in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
88 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
90 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
117 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
121 /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */ in rv770_set_uvd_clocks()
122 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
[all …]
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| /linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip06.dtsi | 23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
[all …]
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| /linux/drivers/usb/host/ |
| H A D | pci-quirks.c | 26 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
27 #define UHCI_USBCMD 0 /* command register */
29 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
30 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
31 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
32 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
33 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
34 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
35 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
37 #define OHCI_CONTROL 0x04
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0x48",
18 "UMask": "0x2"
22 "Counter": "0,1,2,3",
25 "EventCode": "0x48",
29 "UMask": "0x2"
33 "Counter": "0,1,2,3",
[all …]
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| /linux/tools/perf/pmu-events/arch/x86/icelake/ |
| H A D | cache.json | 4 "Counter": "0,1,2,3",
5 "EventCode": "0x51",
9 "UMask": "0x1"
13 "Counter": "0,1,2,3",
14 "EventCode": "0x48",
18 "UMask": "0x2"
22 "Counter": "0,1,2,3",
25 "EventCode": "0x48",
29 "UMask": "0x2"
33 "Counter": "0,1,2,3",
[all …]
|