26 #define UHCI_USBLEGSUP		0xc0		/* legacy support */
27 #define UHCI_USBCMD		0		/* command register */
29 #define UHCI_USBLEGSUP_RWC	0x8f00		/* the R/WC bits */
30 #define UHCI_USBLEGSUP_RO	0x5040		/* R/O and reserved bits */
31 #define UHCI_USBCMD_RUN		0x0001		/* RUN/STOP bit */
32 #define UHCI_USBCMD_HCRESET	0x0002		/* Host Controller reset */
33 #define UHCI_USBCMD_EGSM	0x0008		/* Global Suspend Mode */
34 #define UHCI_USBCMD_CONFIGURE	0x0040		/* Config Flag */
35 #define UHCI_USBINTR_RESUME	0x0002		/* Resume interrupt enable */
37 #define OHCI_CONTROL		0x04
38 #define OHCI_CMDSTATUS		0x08
39 #define OHCI_INTRSTATUS		0x0c
40 #define OHCI_INTRENABLE		0x10
41 #define OHCI_INTRDISABLE	0x14
42 #define OHCI_FMINTERVAL		0x34
44 #define OHCI_HCR		(1 << 0)	/* host controller reset */
50 #define EHCI_HCC_PARAMS		0x08		/* extended capabilities */
51 #define EHCI_USBCMD		0		/* command register */
52 #define EHCI_USBCMD_RUN		(1 << 0)	/* RUN/STOP bit */
56 #define EHCI_CONFIGFLAG		0x40		/* configured flag register */
57 #define EHCI_USBLEGSUP		0		/* legacy support register */
64 #define ASMT_DATA_WRITE0_REG	0xF8
65 #define ASMT_DATA_WRITE1_REG	0xFC
66 #define ASMT_CONTROL_REG	0xE0
67 #define ASMT_CONTROL_WRITE_BIT	0x02
68 #define ASMT_WRITEREG_CMD	0x10423
69 #define ASMT_FLOWCTL_ADDR	0xFA30
70 #define ASMT_FLOWCTL_DATA	0xBA
71 #define ASMT_PSEUDO_DATA	0
74 #define USB_INTEL_XUSB2PR      0xD0
75 #define USB_INTEL_USB2PRM      0xD4
76 #define USB_INTEL_USB3_PSSEN   0xD8
77 #define USB_INTEL_USB3PRM      0xDC
81 #define	AB_REG_BAR_LOW		0xe0
82 #define	AB_REG_BAR_HIGH		0xe1
83 #define	AB_REG_BAR_SB700	0xf0
84 #define	AB_INDX(addr)		((addr) + 0x00)
85 #define	AB_DATA(addr)		((addr) + 0x04)
86 #define	AX_INDXC		0x30
87 #define	AX_DATAC		0x34
89 #define PT_ADDR_INDX		0xE8
90 #define PT_READ_INDX		0xE4
91 #define PT_SIG_1_ADDR		0xA520
92 #define PT_SIG_2_ADDR		0xA521
93 #define PT_SIG_3_ADDR		0xA522
94 #define PT_SIG_4_ADDR		0xA523
95 #define PT_SIG_1_DATA		0x78
96 #define PT_SIG_2_DATA		0x56
97 #define PT_SIG_3_DATA		0x34
98 #define PT_SIG_4_DATA		0x12
99 #define PT4_P1_REG		0xB521
100 #define PT4_P2_REG		0xB522
101 #define PT2_P1_REG		0xD520
102 #define PT2_P2_REG		0xD521
103 #define PT1_P1_REG		0xD522
104 #define PT1_P2_REG		0xD523
106 #define	NB_PCIE_INDX_ADDR	0xe0
107 #define	NB_PCIE_INDX_DATA	0xe4
108 #define	PCIE_P_CNTL		0x10040
109 #define	BIF_NB			0x10002
110 #define	NB_PIF0_PWRDOWN_0	0x01100012
111 #define	NB_PIF0_PWRDOWN_1	0x01100013
117 	NOT_AMD_CHIPSET = 0,
151  * Returns: 1 if it is an AMD chipset, 0 otherwise.
155 	u8 rev = 0;  in amd_chipset_sb_type_init()
162 		if (rev >= 0x10 && rev <= 0x1f)  in amd_chipset_sb_type_init()
164 		else if (rev >= 0x30 && rev <= 0x3f)  in amd_chipset_sb_type_init()
166 		else if (rev >= 0x40 && rev <= 0x4f)  in amd_chipset_sb_type_init()
174 			if (rev >= 0x11 && rev <= 0x14)  in amd_chipset_sb_type_init()
176 			else if (rev >= 0x15 && rev <= 0x18)  in amd_chipset_sb_type_init()
178 			else if (rev >= 0x39 && rev <= 0x3a)  in amd_chipset_sb_type_init()
182 							  0x145c, NULL);  in amd_chipset_sb_type_init()
188 				return 0;  in amd_chipset_sb_type_init()
201 	pci_read_config_word(pdev, 0x50, &misc);  in sb800_prefetch()
202 	if (on == 0)  in sb800_prefetch()
203 		pci_write_config_word(pdev, 0x50, misc & 0xfcff);  in sb800_prefetch()
205 		pci_write_config_word(pdev, 0x50, misc | 0x0300);  in sb800_prefetch()
217 	if (amd_chipset.probe_count > 0) {  in usb_amd_find_chipset_info()
230 		info.need_pll_quirk = info.sb_type.rev <= 0x3B;  in usb_amd_find_chipset_info()
250 	info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);  in usb_amd_find_chipset_info()
254 		info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);  in usb_amd_find_chipset_info()
259 						     0x9600, NULL);  in usb_amd_find_chipset_info()
270 	if (amd_chipset.probe_count > 0) {  in usb_amd_find_chipset_info()
298 	return 0;  in usb_hcd_amd_remote_wakeup_quirk()
311 			 rev >= 0x3a && rev <= 0x3b);  in usb_amd_hang_symptom_quirk()
343 	u32 bit = disable ? 0 : 1;  in usb_amd_quirk_pll()
356 		if (amd_chipset.isoc_reqs > 0) {  in usb_amd_quirk_pll()
365 		outb_p(AB_REG_BAR_LOW, 0xcd6);  in usb_amd_quirk_pll()
366 		addr_low = inb_p(0xcd7);  in usb_amd_quirk_pll()
367 		outb_p(AB_REG_BAR_HIGH, 0xcd6);  in usb_amd_quirk_pll()
368 		addr_high = inb_p(0xcd7);  in usb_amd_quirk_pll()
371 		outl_p(0x30, AB_INDX(addr));  in usb_amd_quirk_pll()
372 		outl_p(0x40, AB_DATA(addr));  in usb_amd_quirk_pll()
373 		outl_p(0x34, AB_INDX(addr));  in usb_amd_quirk_pll()
376 			amd_chipset.sb_type.rev <= 0x3b) {  in usb_amd_quirk_pll()
380 		outl(0x40, AB_DATA(addr));  in usb_amd_quirk_pll()
389 		val &= ~0x08;  in usb_amd_quirk_pll()
392 		val |= 0x08;  in usb_amd_quirk_pll()
432 			val &= ~(0x3f << 7);  in usb_amd_quirk_pll()
434 			val |= 0x3f << 7;  in usb_amd_quirk_pll()
445 			val &= ~(0x3f << 7);  in usb_amd_quirk_pll()
447 			val |= 0x3f << 7;  in usb_amd_quirk_pll()
465 	usb_amd_quirk_pll(0);  in usb_amd_quirk_pll_enable()
477 	if (amd_chipset.probe_count > 0) {  in usb_amd_dev_put()
488 	amd_chipset.nb_type = 0;  in usb_amd_dev_put()
489 	memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));  in usb_amd_dev_put()
490 	amd_chipset.isoc_reqs = 0;  in usb_amd_dev_put()
539 	case 0x43b9:  in usb_amd_pt_check_port()
540 	case 0x43ba:  in usb_amd_pt_check_port()
542 	 * device is AMD_PROMONTORYA_4(0x43b9) or PROMONTORYA_3(0x43ba)  in usb_amd_pt_check_port()
543 	 * PT4_P1_REG bits[7..1] represents USB2.0 ports 6 to 0  in usb_amd_pt_check_port()
544 	 * PT4_P2_REG bits[6..0] represents ports 13 to 7  in usb_amd_pt_check_port()
554 	case 0x43bb:  in usb_amd_pt_check_port()
556 	 * device is AMD_PROMONTORYA_2(0x43bb)  in usb_amd_pt_check_port()
557 	 * PT2_P1_REG bits[7..5] represents USB2.0 ports 2 to 0  in usb_amd_pt_check_port()
558 	 * PT2_P2_REG bits[5..0] represents ports 9 to 3  in usb_amd_pt_check_port()
568 	case 0x43bc:  in usb_amd_pt_check_port()
570 	 * device is AMD_PROMONTORYA_1(0x43bc)  in usb_amd_pt_check_port()
571 	 * PT1_P1_REG[7..4] represents USB2.0 ports 3 to 0  in usb_amd_pt_check_port()
572 	 * PT1_P2_REG[5..0] represents ports 9 to 4  in usb_amd_pt_check_port()
598 	for (retry_count = 1000; retry_count > 0; --retry_count) {  in usb_asmedia_wait_write()
602 		if (value == 0xff) {  in usb_asmedia_wait_write()
607 		if ((value & ASMT_CONTROL_WRITE_BIT) == 0)  in usb_asmedia_wait_write()
608 			return 0;  in usb_asmedia_wait_write()
619 	if (usb_asmedia_wait_write(pdev) != 0)  in usb_asmedia_modifyflowcontrol()
627 	if (usb_asmedia_wait_write(pdev) != 0)  in usb_asmedia_modifyflowcontrol()
672 	outw(0, base + UHCI_USBINTR);  in uhci_reset_hc()
673 	outw(0, base + UHCI_USBCMD);  in uhci_reset_hc()
681  * Returns: 1 if the controller was reset, 0 otherwise.
700 		dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",  in uhci_check_and_reset_hc()
708 		dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",  in uhci_check_and_reset_hc()
715 		dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",  in uhci_check_and_reset_hc()
719 	return 0;  in uhci_check_and_reset_hc()
732 	unsigned long base = 0;  in quirk_usb_handoff_uhci()
738 	for (i = 0; i < PCI_STD_NUM_BARS; i++)  in quirk_usb_handoff_uhci()
763 	u32 fminterval = 0;  in quirk_usb_handoff_ohci()
767 	if (!mmio_resource_enabled(pdev, 0))  in quirk_usb_handoff_ohci()
770 	base = pci_ioremap_bar(pdev, 0);  in quirk_usb_handoff_ohci()
778 	if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)  in quirk_usb_handoff_ohci()
793 		while (wait_time > 0 &&  in quirk_usb_handoff_ohci()
798 		if (wait_time <= 0)  in quirk_usb_handoff_ohci()
806 	writel((u32) ~0, base + OHCI_INTRDISABLE);  in quirk_usb_handoff_ohci()
819 	for (cnt = 30; cnt > 0; --cnt) {	/* ... allow extra time */  in quirk_usb_handoff_ohci()
820 		if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)  in quirk_usb_handoff_ohci()
869 	int try_handoff = 1, tried_handoff = 0;  in ehci_bios_handoff()
877 	if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||  in ehci_bios_handoff()
878 			pdev->device == 0x27cc)) {  in ehci_bios_handoff()
880 			try_handoff = 0;  in ehci_bios_handoff()
886 #if 0  in ehci_bios_handoff()
910 		while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {  in ehci_bios_handoff()
926 		pci_write_config_byte(pdev, offset + 2, 0);  in ehci_bios_handoff()
930 	pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);  in ehci_bios_handoff()
936 		writel(0, op_reg_base + EHCI_CONFIGFLAG);  in ehci_bios_handoff()
946 	if (!mmio_resource_enabled(pdev, 0))  in quirk_usb_disable_ehci()
949 	base = pci_ioremap_bar(pdev, 0);  in quirk_usb_disable_ehci()
964 	 * register should be 0x0 but it reads as 0xa0.  So clear it to  in quirk_usb_disable_ehci()
967 	if (pdev->vendor == PCI_VENDOR_ID_LOONGSON && pdev->device == 0x7a14)  in quirk_usb_disable_ehci()
968 		hcc_params &= ~(0xffL << 8);  in quirk_usb_disable_ehci()
970 	offset = (hcc_params >> 8) & 0xff;  in quirk_usb_disable_ehci()
974 		switch (cap & 0xff) {  in quirk_usb_disable_ehci()
978 		case 0: /* Illegal reserved cap, set cap=0 so we exit */  in quirk_usb_disable_ehci()
979 			cap = 0;  in quirk_usb_disable_ehci()
984 				 cap & 0xff);  in quirk_usb_disable_ehci()
986 		offset = (cap >> 8) & 0xff;  in quirk_usb_disable_ehci()
995 	if ((val & EHCI_USBSTS_HALTED) == 0) {  in quirk_usb_disable_ehci()
1002 			writel(0x3f, op_reg_base + EHCI_USBSTS);  in quirk_usb_disable_ehci()
1006 			if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {  in quirk_usb_disable_ehci()
1009 		} while (wait_time > 0);  in quirk_usb_disable_ehci()
1011 	writel(0, op_reg_base + EHCI_USBINTR);  in quirk_usb_disable_ehci()
1012 	writel(0x3f, op_reg_base + EHCI_USBSTS);  in quirk_usb_disable_ehci()
1026  * Returns 0 when the mask bits have the value done.
1068 	    xhci_pdev->subsystem_device == 0x90a8)  in usb_enable_intel_xhci_ports()
1102 	dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",  in usb_enable_intel_xhci_ports()
1115 		"USB 3.0 ports that are now enabled under xHCI: 0x%x\n",  in usb_enable_intel_xhci_ports()
1125 	dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",  in usb_enable_intel_xhci_ports()
1138 		"USB 2.0 ports that are now switched over to xHCI: 0x%x\n",  in usb_enable_intel_xhci_ports()
1145 	pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);  in usb_disable_xhci_ports()
1146 	pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);  in usb_disable_xhci_ports()
1165 	int len = pci_resource_len(pdev, 0);  in quirk_usb_handoff_xhci()
1167 	if (!mmio_resource_enabled(pdev, 0))  in quirk_usb_handoff_xhci()
1170 	base = ioremap(pci_resource_start(pdev, 0), len);  in quirk_usb_handoff_xhci()
1178 	ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);  in quirk_usb_handoff_xhci()
1191 	if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||  in quirk_usb_handoff_xhci()
1193 			 && pdev->device == 0x0014)) {  in quirk_usb_handoff_xhci()
1204 				0, 1000000, 10);  in quirk_usb_handoff_xhci()
1232 	timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,  in quirk_usb_handoff_xhci()
1238 			 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",  in quirk_usb_handoff_xhci()
1253 			 "xHCI HW did not halt within %d usec status = 0x%x\n",  in quirk_usb_handoff_xhci()
1269 	if (pdev->vendor == 0x184e)	/* vendor Netlogic */  in quirk_usb_early_handoff()
1276 	if (pdev->vendor == PCI_VENDOR_ID_VIA && pdev->device == 0x3483) {  in quirk_usb_early_handoff()
1290 	if (pci_enable_device(pdev) < 0) {  in quirk_usb_early_handoff()