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/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpsoc_reset_conf_masks.h24 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
25 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1
28 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
29 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1
32 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
33 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1
36 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
37 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1
40 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
41 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/
H A Dgaudi2_special_blocks.h16 { GAUDI2_BLOCK_TYPE_TPC, 0xfc008000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
17 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00a000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
18 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00b000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
19 { GAUDI2_BLOCK_TYPE_TPC, 0xfc00c000, 4, 6, 0, 0x200000, 0x10000, 0x0 }, \
20 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc080000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
21 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc081000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
22 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc083000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
23 { GAUDI2_BLOCK_TYPE_HMMU, 0xfc084000, 4, 4, 0, 0x200000, 0x10000, 0x0 }, \
24 { GAUDI2_BLOCK_TYPE_MME, 0xfc0c8000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
25 { GAUDI2_BLOCK_TYPE_MME, 0xfc0c9000, 4, 0, 0, 0x200000, 0x0, 0x0 }, \
[all …]
/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-lsio.dtsi12 #clock-cells = <0>;
21 ranges = <0x5d000000 0x0 0x5d000000 0x1000000>,
22 <0x08000000 0x0 0x08000000 0x10000000>;
26 reg = <0x5d000000 0x10000>;
39 reg = <0x5d010000 0x10000>;
52 reg = <0x5d020000 0x10000>;
65 reg = <0x5d030000 0x10000>;
77 reg = <0x5d080000 0x10000>;
87 reg = <0x5d090000 0x10000>;
97 reg = <0x5d0a0000 0x10000>;
[all …]
H A Dimx8-ss-audio.dtsi14 #clock-cells = <0>;
21 #clock-cells = <0>;
22 clock-frequency = <0>;
28 #clock-cells = <0>;
29 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
43 clock-frequency = <0>;
49 #clock-cells = <0>;
[all …]
H A Dimx8-ss-dma.dtsi13 #clock-cells = <0>;
22 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
26 reg = <0x5a000000 0x10000>;
28 #size-cells = <0>;
37 dmas = <&edma2 1 0 0>, <&edma2 0 0 FSL_EDMA_RX>;
44 reg = <0x5a010000 0x10000>;
46 #size-cells = <0>;
55 dmas = <&edma2 3 0 0>, <&edma2 2 0 FSL_EDMA_RX>;
62 reg = <0x5a020000 0x10000>;
64 #size-cells = <0>;
[all …]
H A Dimx8-ss-conn.dtsi12 #clock-cells = <0>;
19 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #clock-cells = <0>;
42 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
46 reg = <0x5b0d0000 0x200>;
50 fsl,usbmisc = <&usbmisc1 0>;
52 ahb-burst-config = <0x0>;
53 tx-burst-size-dword = <0x10>;
54 rx-burst-size-dword = <0x10>;
[all …]
H A Dfsl-ls1043a.dtsi37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
[all …]
H A Dimx8qxp-ss-hsio.dtsi10 reg = <0x5f090000 0x10000>;
25 reg = <0x5f1a0000 0x10000>,
26 <0x5f120000 0x10000>,
27 <0x5f140000 0x10000>,
28 <0x5f160000 0x10000>;
H A Dimx8dxl-ss-hsio.dtsi9 reg = <0x5f090000 0x10000>;
24 reg = <0x5f1a0000 0x10000>,
25 <0x5f120000 0x10000>,
26 <0x5f140000 0x10000>,
27 <0x5f160000 0x10000>;
45 interrupt-map = <0 0 0 1 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
46 <0 0 0 2 &gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
47 <0 0 0 3 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
48 <0 0 0 4 &gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
49 interrupt-map-mask = <0 0 0 0x7>;
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
91 - description: common_s0 DSS Shared common 0
112 port@0:
158 reg = <0x04a00000 0x10000>, /* common_m */
159 <0x04a10000 0x10000>, /* common_s0*/
160 <0x04b00000 0x10000>, /* common_s1*/
161 <0x04b10000 0x10000>, /* common_s2*/
162 <0x04a20000 0x10000>, /* vidl1 */
163 <0x04a30000 0x10000>, /* vidl2 */
164 <0x04a50000 0x10000>, /* vid1 */
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmscc,vsc7514-switch.yaml132 reg = <0x1010000 0x10000>,
133 <0x1030000 0x10000>,
134 <0x1080000 0x100>,
135 <0x10e0000 0x10000>,
136 <0x11e0000 0x100>,
137 <0x11f0000 0x100>,
138 <0x1200000 0x100>,
139 <0x1210000 0x100>,
140 <0x1220000 0x100>,
141 <0x1230000 0x100>,
[all …]
/linux/drivers/mtd/chips/
H A Djedec_probe.c27 #define AM29DL800BB 0x22CB
28 #define AM29DL800BT 0x224A
30 #define AM29F800BB 0x2258
31 #define AM29F800BT 0x22D6
32 #define AM29LV400BB 0x22BA
33 #define AM29LV400BT 0x22B9
34 #define AM29LV800BB 0x225B
35 #define AM29LV800BT 0x22DA
36 #define AM29LV160DT 0x22C4
37 #define AM29LV160DB 0x2249
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
205 cpu_opp: opp-table-0 {
265 #clock-cells = <0>;
270 #clock-cells = <0>;
276 #clock-cells = <0>;
283 #clock-cells = <0>;
290 #clock-cells = <0>;
296 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8280xp-el2.dtso21 iommu-map = <0 &pcie_smmu 0x20000 0x10000>;
25 iommu-map = <0 &pcie_smmu 0x30000 0x10000>;
29 iommu-map = <0 &pcie_smmu 0x40000 0x10000>;
33 iommu-map = <0 &pcie_smmu 0x50000 0x10000>;
37 iommu-map = <0 &pcie_smmu 0x60000 0x10000>;
/linux/arch/arm64/boot/dts/amd/
H A Delba-flash-parts.dtsi11 partition@0 {
13 reg = <0x0 0x10000>;
19 reg = <0x10000 0xfff0000>;
24 reg = <0xf0000 0x10000>;
29 reg = <0x100000 0x80000>;
34 reg = <0x180000 0x200000>;
39 reg = <0x380000 0x10000>;
44 reg = <0x390000 0x10000>;
49 reg = <0x400000 0x3c00000>;
54 reg = <0x4010000 0x20000>;
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hdr.h21 NETXEN_HW_H0_CH_HUB_ADR = 0x05,
22 NETXEN_HW_H1_CH_HUB_ADR = 0x0E,
23 NETXEN_HW_H2_CH_HUB_ADR = 0x03,
24 NETXEN_HW_H3_CH_HUB_ADR = 0x01,
25 NETXEN_HW_H4_CH_HUB_ADR = 0x06,
26 NETXEN_HW_H5_CH_HUB_ADR = 0x07,
27 NETXEN_HW_H6_CH_HUB_ADR = 0x08
30 /* Hub 0 */
32 NETXEN_HW_MN_CRB_AGT_ADR = 0x15,
33 NETXEN_HW_MS_CRB_AGT_ADR = 0x25
[all …]
/linux/drivers/mtd/devices/
H A Dspear_smi.c51 #define SMI_CR1 0x0 /* SMI control register 1 */
52 #define SMI_CR2 0x4 /* SMI control register 2 */
53 #define SMI_SR 0x8 /* SMI status register */
54 #define SMI_TR 0xC /* SMI transmit register */
55 #define SMI_RR 0x10 /* SMI receive register */
58 #define BANK_EN (0xF << 0) /* enables all banks */
59 #define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */
60 #define SW_MODE (0x1 << 28) /* enables SW Mode */
61 #define WB_MODE (0x1 << 29) /* Write Burst Mode */
62 #define FAST_MODE (0x1 << 15) /* Fast Mode */
[all …]
/linux/Documentation/devicetree/bindings/mips/cavium/
H A Dbootbus.txt52 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
71 reg = <0x11800 0x00000000 0x0 0x200>;
76 ranges = <0 0 0x0 0x1f400000 0xc00000>,
77 <1 0 0x10000 0x30000000 0>,
78 <2 0 0x10000 0x40000000 0>,
79 <3 0 0x10000 0x50000000 0>,
80 <4 0 0x0 0x1d020000 0x10000>,
81 <5 0 0x0 0x1d040000 0x10000>,
82 <6 0 0x0 0x1d050000 0x10000>,
83 <7 0 0x10000 0x90000000 0>;
[all …]
/linux/drivers/bcma/
H A Ddriver_chipcommon_sflash.c16 .end = 0,
34 { "M25P20", 0x11, 0x10000, 4, },
35 { "M25P40", 0x12, 0x10000, 8, },
37 { "M25P16", 0x14, 0x10000, 32, },
38 { "M25P32", 0x15, 0x10000, 64, },
39 { "M25P64", 0x16, 0x10000, 128, },
40 { "M25FL128", 0x17, 0x10000, 256, },
41 { "MX25L25635F", 0x18, 0x10000, 512, },
46 { "SST25WF512", 1, 0x1000, 16, },
47 { "SST25VF512", 0x48, 0x1000, 16, },
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dmorello.dtsi16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
38 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
45 clocks = <&scmi_dvfs 0>;
51 cache-size = <0x100000>;
61 reg = <0x0 0x100>;
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5260.dtsi35 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x0>;
73 reg = <0x1>;
80 reg = <0x100>;
87 reg = <0x101>;
94 reg = <0x102>;
101 reg = <0x103>;
114 reg = <0x10010000 0x10000>;
128 reg = <0x10200000 0x10000>;
[all …]

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