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/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8851b_rfk_table.c8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-ip6.c108 for (i = 0; i < len; i++) { in ip6_finddst()
122 * Accordingly, the final DA is encoded in srh_segments[0] in ip6_finddst()
186 memset(&ph, 0, sizeof(ph)); in nextproto6_cksum()
212 vec[0].ptr = (const uint8_t *)(void *)&ph; in nextproto6_cksum()
213 vec[0].len = sizeof(ph); in nextproto6_cksum()
233 int fragmented = 0; in ip6_print()
258 * message, Code 0, should be sent to the packet's source, pointing in ip6_print()
264 * If the payload length is 0, we temporarily just set the total in ip6_print()
273 if (payload_len != 0) { in ip6_print()
290 if (flow & 0x0ff00000) in ip6_print()
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_reg.h29 #define R88E_BB_PAD_CTRL 0x064
30 #define R88E_HIMR 0x0b0
31 #define R88E_HISR 0x0b4
32 #define R88E_HIMRE 0x0b8
33 #define R88E_HISRE 0x0bc
34 #define R88E_XCK_OUT_CTRL 0x07c
36 #define R88E_32K_CTRL 0x194
37 #define R88E_HMEBOX_EXT(idx) (0x1f0 + (idx) * 4)
39 #define R88E_TXPKTBUF_BCNQ1_BDNY 0x457
40 #define R88E_MACID_NO_LINK 0x484
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8992-lg-h815.dts26 qcom,msm-id = <0xfb 0x0>;
27 qcom,pmic-id = <0x10009 0x1000a 0x0 0x0>;
28 qcom,board-id = <0xb64 0x0>;
39 reg = <0x0 0x06000000 0x0 0x00001000>;
45 reg = <0x0 0x0ff00000 0x0 0x00100000>;
46 console-size = <0x20000>;
47 pmsg-size = <0x20000>;
48 record-size = <0x10000>;
49 ecc-size = <0x10>;
53 reg = <0x0 0x03400000 0x0 0x00c00000>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212desc.h32 uint32_t ds_ctl0; /* DMA control 0 */
38 uint32_t status0;/* DMA status 0 */
42 uint32_t status0;/* DMA status 0 */
58 #define AR_FrameLen 0x00000fff /* frame length */
60 #define AR_XmitPower 0x003f0000 /* transmit power control */
62 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
63 #define AR_VEOL 0x00800000 /* virtual end-of-list */
64 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
65 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
67 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
[all …]
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx7d.dtsi17 cpu0: cpu@0 {
53 opp-supported-hw = <0xd>, <0x7>;
61 opp-supported-hw = <0xc>, <0x7>;
69 opp-supported-hw = <0x8>, <0x3>;
78 #phy-cells = <0>;
84 reg = <0x3007d000 0x100
[all...]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-msm8926-htc-memul.dts50 reg = <0x05b00000 0x200000>;
55 reg = <0x07500000 0xb00000>;
60 reg = <0x08000000 0x4f00000>;
65 reg = <0x0cf00000 0x200000>;
70 reg = <0x0d100000 0x3a000>;
75 reg = <0x0d13a000 0xc6000>;
80 reg = <0x0d200000 0x650000>;
85 reg = <0x0d850000 0x3b0000>;
90 reg = <0x0dc00000 0x1400000>;
95 reg = <0x0f000000 0x500000>;
[all …]
H A Dqcom-ipq8064.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
54 polling-delay-passive = <0>;
55 polling-delay = <0>;
56 thermal-sensors = <&tsens 0>;
74 polling-delay-passive = <0>;
75 polling-delay = <0>;
94 polling-delay-passive = <0>;
95 polling-delay = <0>;
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5416/
H A Dar5416desc.h29 #define _get_index(_ah) ( IS_5416V1(_ah) ? -4 : 0 )
68 uint32_t ds_ctl0; /* DMA control 0 */
104 #define AR_FrameLen 0x00000fff
105 #define AR_VirtMoreFrag 0x00001000
106 #define AR_TxCtlRsvd00 0x0000e000
107 #define AR_XmitPower 0x003f0000
109 #define AR_RTSEnable 0x00400000
110 #define AR_VEOL 0x00800000
111 #define AR_ClrDestMask 0x01000000
112 #define AR_TxCtlRsvd01 0x1e000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/davinci/
H A Dda850-lcdk.dts24 /* 128 MB DDR2 SDRAM @ 0xc0000000 */
25 reg = <0xc0000000 0x08000000>;
35 reg = <0xc3000000 0x1000000>;
122 #size-cells = <0>;
126 #size-cells = <0>;
128 port@0 {
129 reg = <0>;
205 0x0
[all...]
H A Dda850-evm.dts29 pinctrl-0 = <&ecap2_pins>;
37 pwms = <&ecap2 0 50000 0>;
38 brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
45 pinctrl-0 = <&lcd_pins>;
56 ac-bias-intrpt = <0>;
59 fdd = <0x80>;
60 sync-edge = <0>;
62 raster-order = <0>;
63 fifo-th = <0>;
78 hsync-active = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dqcom,pcie.txt321 reg = <0x1b500000 0x1000
322 0x1b502000 0x80
323 0x1b600000 0x100
324 0x0ff00000 0x100000>;
327 linux,pci-domain = <0>;
328 bus-range = <0x00 0xff>;
332 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
333 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
337 interrupt-map-mask = <0 0 0 0x7>;
338 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
[all …]
H A Dqcom,pcie.yaml588 reg = <0x1b500000 0x1000>,
589 <0x1b502000 0x80>,
590 <0x1b600000 0x100>,
591 <0x0ff00000 0x100000>;
594 linux,pci-domain = <0>;
595 bus-range = <0x00 0xff>;
599 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000>,
600 <0x82000000 0 0 0x08000000 0 0x07e00000>;
604 interrupt-map-mask = <0 0 0 0x7>;
605 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/cddl/lib/libdtrace/
H A Dip.d127 inline short IPPROTO_IP = 0;
171 inline uint8_t INP_IPV4 = 0x01;
172 inline uint8_t INP_IPV6 = 0x02;
213 cs_pid = 0;
214 cs_zoneid = 0;
221 cs_pid = 0; /* XXX */
222 cs_zoneid = 0;
227 ip_ver = p == NULL ? 0 : ((struct ip *)p)->ip_v;
228 ip_plength = p == NULL ? 0 :
244 ip_ver = m == NULL ? 0 : ((struct ip *)m->m_data)->ip_v;
[all …]
/freebsd/sys/dev/qlxgb/
H A Dqla_misc.c54 #define Q8_ADDR_UNDEFINED 0xFFFFFFFF
61 Q8_ADDR_UNDEFINED, /* 0x00 */
62 0x77300000, /* 0x01 */
63 0x29500000, /* 0x02 */
64 0x2A500000, /* 0x03 */
65 Q8_ADDR_UNDEFINED, /* 0x04 */
66 0x0D000000, /* 0x05 */
67 0x1B100000, /* 0x06 */
68 0x0E600000, /* 0x07 */
69 0x0E000000, /* 0x08 */
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/
H A DELF.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
45 static const char ElfMagic[] = {0x7f, 'E', 'L', 'F', '\0'};
49 EI_MAG0 = 0, // File identification index.
79 return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0; in checkMagic()
105 return (memcmp(e_ident, ElfMagic, strlen(ElfMagic))) == 0; in checkMagic()
116 ET_NONE = 0, // No file type
121 ET_LOOS = 0xfe00, // Beginning of operating system-specific codes
122 ET_HIOS = 0xfeff, // Operating system-specific
123 ET_LOPROC = 0xff00, // Beginning of processor-specific codes
124 ET_HIPROC = 0xffff // Processor-specific
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300desc.h94 #define AR_desc_len 0x000000ff
95 #define AR_rx_priority 0x00000100
96 #define AR_tx_qcu_num 0x00000f00
98 #define AR_ctrl_stat 0x00004000
100 #define AR_tx_rx_desc 0x00008000
102 #define AR_desc_id 0xffff0000
113 #define AR_buf_len 0x0fff0000
117 #define AR_tx_desc_id 0xffff0000
119 #define AR_tx_ptr_chk_sum 0x0000ffff
122 #define AR_frame_len 0x00000fff
[all …]
/freebsd/sys/dev/bfe/
H A Dif_bfereg.h32 #define BFE_PCI_MEMLO 0x10
33 #define BFE_PCI_MEMHIGH 0x14
34 #define BFE_PCI_INTLINE 0x3C
37 #define BFE_DEVCTRL 0x00000000 /* Device Control */
38 #define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
39 #define BFE_IPP 0x00000400 /* Internal EPHY Present */
40 #define BFE_EPR 0x00008000 /* EPHY Reset */
41 #define BFE_PME 0x00001000 /* PHY Mode Enable */
42 #define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
43 #define BFE_PADDR 0x0007c000 /* PHY Address */
[all …]
/freebsd/sys/arm/arm/
H A Ddisassem.c76 * m - m register (bits 0-3)
81 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * t - thumb branch address (bits 24, 0-23)
84 * k - breakpoint comment (bits 0-3, 8-19)
87 * c - comment field bits(0-23)
112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
114 { 0x0f000000, 0x0f000000, "swi", "c" },
115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
116 { 0x0f000000, 0x0a000000, "b", "b" },
[all …]
/freebsd/sys/sys/
H A Delf_common.h59 #define ODK_NULL 0 /* undefined */
75 #define OEX_FPU_MIN 0x0000001f /* min FPU exception required */
76 #define OEX_FPU_MAX 0x00001f00 /* max FPU exception allowed */
77 #define OEX_PAGE0 0x00010000 /* page zero must be mapped */
78 #define OEX_SMM 0x00020000 /* run in sequential memory mode */
79 #define OEX_PRECISEFP 0x00040000 /* run in precise FP exception mode */
80 #define OEX_DISMISS 0x00080000 /* dismiss invalid address traps */
85 #define OPAD_PREFIX 0x0001
86 #define OPAD_POSTFIX 0x0002
87 #define OPAD_SYMBOL 0x0004
[all …]
/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsaioctlcmd.c83 bit32 i, tcid_processor_cmd = 0; in saFwProfile()
177 for (i = 0; i < FWPROFILE_IOMB_RESERVED_LEN; i ++) in saFwProfile()
179 pPayload->reserved0[i] = 0; in saFwProfile()
342 for (i = 0; i < FWFLASH_IOMB_RESERVED_LEN; i ++) { in saFwFlashUpdate()
343 pPayload->reserved0[i] = 0; in saFwFlashUpdate()
469 si_memset(pPayload, 0, sizeof(agsaFwFlashOpExt_t)); in saFlashExtExecute()
630 SA_DBG1(("mpiFwFlashUpdateRsp: status = 0x%x\n",status)); in mpiFwFlashUpdateRsp()
686 SA_DBG1(("mpiFwExtFlashUpdateRsp: status = 0x%x\n",Status)); in mpiFwExtFlashUpdateRsp()
723 bit32 value = 0, value1 = 0; in saGetControllerInfo()
731 si_memset(controllerInfo, 0, sizeof(agsaControllerInfo_t)); in saGetControllerInfo()
[all …]

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