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/freebsd/contrib/opencsd/decoder/source/i_dec/
H A Dtrc_idec_arminst.cpp48 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_direct_branch()
50 if ((inst & 0xfe000000) == 0xfa000000){ in inst_ARM_is_direct_branch()
53 is_direct_branch = 0; in inst_ARM_is_direct_branch()
55 } else if ((inst & 0x0e000000) == 0x0a000000) { in inst_ARM_is_direct_branch()
58 is_direct_branch = 0; in inst_ARM_is_direct_branch()
65 if ( ((inst & 0xf0000000) != 0xf0000000) && in inst_ARM_wfiwfe()
66 ((inst & 0x0ffffffe) == 0x0320f002) in inst_ARM_wfiwfe()
70 return 0; in inst_ARM_wfiwfe()
76 if ((inst & 0xf0000000) == 0xf0000000) { in inst_ARM_is_indirect_branch()
78 if ((inst & 0xfe500000) == 0xf8100000) { in inst_ARM_is_indirect_branch()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
H A Dk3-am62.dtsi55 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
56 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
57 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
58 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
59 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
60 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
61 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
62 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
63 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
64 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j722s.dtsi24 #size-cells = <0>;
46 cpu0: cpu@0 {
48 reg = <0x000>;
51 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
58 clocks = <&k3_clks 135 0>;
63 reg = <0x001>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
73 clocks = <&k3_clks 136 0>;
[all …]
H A Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mscc/
H A Docelot_pcb123.dts15 memory@0 {
17 reg = <0x0 0x0e000000>;
32 flash@0 {
35 reg = <0>;
H A Docelot_pcb120.dts18 memory@0 {
20 reg = <0x0 0x0e000000>;
43 pinctrl-0 = <&miim1_pins>, <&phy_int_pins>, <&phy_load_save_pins>;
45 phy7: ethernet-phy@0 {
46 reg = <0>;
/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra-ccplex-cluster.yaml21 pattern: "ccplex@([0-9a-f]+)$"
48 reg = <0x0e000000 0x5ffff>;
/freebsd/sys/contrib/device-tree/src/mips/brcm/
H A Dbcm3384_viper.dtsi7 memory@0 {
11 reg = <0x06000000 0x02000000>,
12 <0x0e000000 0x02000000>;
17 #size-cells = <0>;
22 cpu@0 {
25 reg = <0>;
30 #address-cells = <0>;
40 #clock-cells = <0>;
59 reg = <0x14e00048 0x4 0x14e0004c 0x4>,
60 <0x14e00350 0x4 0x14e00354 0x4>;
[all …]
/freebsd/sys/dev/igc/
H A Digc_i225.h40 #define NVM_INIT_CTRL_2_DEFAULT_I225 0X7243
41 #define NVM_INIT_CTRL_4_DEFAULT_I225 0x00C1
42 #define NVM_LED_1_CFG_DEFAULT_I225 0x0184
43 #define NVM_LED_0_2_CFG_DEFAULT_I225 0x200C
45 #define IGC_MRQC_ENABLE_RSS_4Q 0x00000002
46 #define IGC_MRQC_ENABLE_VMDQ 0x00000003
47 #define IGC_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005
48 #define IGC_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
49 #define IGC_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
50 #define IGC_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6dl-colibri-eval-v3.dts37 #clock-cells = <0>;
47 mcp251x0: mcp251x@0 {
51 interrupts = <27 0x2>;
52 reg = <0>;
67 reg = <0x68>;
73 pinctrl-0 = <
132 ranges = <0 0 0x08000000 0x02000000
133 1 0 0x0a000000 0x02000000
134 2 0 0x0c000000 0x02000000
135 3 0 0x0e000000 0x02000000>;
[all …]
H A Dimx53-sk-imx53.dts29 reg = <0x70000000 0x20000000>;
53 pinctrl-0 = <&pinctrl_audmux>;
59 pinctrl-0 = <&pinctrl_can1>;
75 pinctrl-0 = <&pinctrl_ecspi1>;
82 pinctrl-0 = <&pinctrl_ecspi2>;
91 pinctrl-0 = <&pinctrl_esdhc1>;
97 pinctrl-0 = <&pinctrl_fec>;
105 #size-cells = <0>;
107 phy0: ethernet-phy@0 {
108 reg = <0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dimx-weim.txt25 <cs-number> 0 <physical address of mapping> <size>
32 register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
36 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
38 05 128M 0M 0M 0M
39 033 64M 64M 0M 0M
40 0113 64M 32M 32M 0M
44 what bootloader sets up in IOMUXC_GPR1[11:0] will be
75 reg = <0x021b8000 0x4000>;
79 ranges = <0 0 0x08000000 0x08000000>;
82 nor@0,0 {
[all …]
/freebsd/sys/dev/sound/pci/
H A Demuxkireg.h50 #define EMU_PTR 0x00
51 #define EMU_PTR_CHNO_MASK 0x0000003f
52 #define EMU_PTR_ADDR_MASK 0x07ff0000
53 #define EMU_A_PTR_ADDR_MASK 0x0fff0000
55 #define EMU_DATA 0x04
57 #define EMU_IPR 0x08
58 #define EMU_IPR_RATETRCHANGE 0x01000000
59 #define EMU_IPR_FXDSP 0x00800000
60 #define EMU_IPR_FORCEINT 0x00400000
61 #define EMU_PCIERROR 0x00200000
[all …]
/freebsd/sys/dev/cxgbe/firmware/
H A Dt6fw_cfg_hashfilter.txt19 reg[0x10c4] = 0x20000000/0x20000000 # GK_CONTROL, enable 5th thread
21 reg[0x7dc0] = 0x0e2f8849 # TP_SHIFT_CNT
32 # TP number of RX channels (0 = auto)
33 tp_nrxch = 0
38 # TP number of TX channels (0 = auto)
39 tp_ntxch = 0
45 reg[0x7d04] = 0x00010008/0x00010008
48 reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
51 reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
54 reg[0x7d4c] = 0x00010000/0x00010000 # set DisableNewPshFlag
[all …]
/freebsd/sys/dev/e1000/
H A De1000_vf.h44 #define E1000_DEV_ID_82576_VF 0x10CA
45 #define E1000_DEV_ID_I350_VF 0x1520
50 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
51 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
54 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
55 (0x0C00C + ((_n) * 0x40)))
57 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
59 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
60 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
61 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
[all …]
H A De1000_82575.h56 #define E1000_SW_SYNCH_MB 0x00000100
57 #define E1000_STAT_DEV_RST_SET 0x00100000
81 #define E1000_TXD_DTYP_ADV_C 0x2 /* Advanced Context Descriptor */
82 #define E1000_TXD_DTYP_ADV_D 0x3 /* Advanced Data Descriptor */
83 #define E1000_ADV_TXD_CMD_DEXT 0x20 /* Descriptor extension (0 = legacy) */
84 #define E1000_ADV_TUCMD_IPV4 0x2 /* IP Packet Type: 1=IPv4 */
85 #define E1000_ADV_TUCMD_IPV6 0x0 /* IP Packet Type: 0=IPv6 */
86 #define E1000_ADV_TUCMD_L4T_UDP 0x0 /* L4 Packet TYPE of UDP */
87 #define E1000_ADV_TUCMD_L4T_TCP 0x4 /* L4 Packet TYPE of TCP */
88 #define E1000_ADV_TUCMD_MKRREQ 0x10 /* Indicates markers are required */
[all …]
/freebsd/usr.sbin/bhyve/
H A Dahci.h34 #define ATA_DATA 0 /* (RW) data */
37 #define ATA_F_DMA 0x01 /* enable DMA */
38 #define ATA_F_OVL 0x02 /* enable overlap */
46 #define ATA_D_LBA 0x40 /* use LBA addressing */
47 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
52 #define ATA_E_ILI 0x01 /* illegal length */
53 #define ATA_E_NM 0x02 /* no media */
54 #define ATA_E_ABORT 0x04 /* command aborted */
55 #define ATA_E_MCR 0x08 /* media change request */
56 #define ATA_E_IDNF 0x10 /* ID not found */
[all …]
/freebsd/sys/dev/ahci/
H A Dahci.h31 #define ATA_DATA 0 /* (RW) data */
34 #define ATA_F_DMA 0x01 /* enable DMA */
35 #define ATA_F_OVL 0x02 /* enable overlap */
43 #define ATA_D_LBA 0x40 /* use LBA addressing */
44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
49 #define ATA_E_ILI 0x01 /* illegal length */
50 #define ATA_E_NM 0x02 /* no media */
51 #define ATA_E_ABORT 0x04 /* command aborted */
52 #define ATA_E_MCR 0x08 /* media change request */
53 #define ATA_E_IDNF 0x10 /* ID not found */
[all …]
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_mac_regs.h59 uint32_t aFramesTransmittedOK; /* 0x68 */
60 uint32_t aFramesReceivedOK; /* 0x6c */
61 uint32_t aFrameCheckSequenceErrors; /* 0x70 */
62 uint32_t aAlignmentErrors; /* 0x74 */
63 uint32_t aOctetsTransmittedOK; /* 0x78 */
64 uint32_t aOctetsReceivedOK; /* 0x7c */
65 uint32_t aPAUSEMACCtrlFramesTransmitted; /* 0x80 */
66 uint32_t aPAUSEMACCtrlFramesReceived; /* 0x84 */
67 uint32_t ifInErrors ; /* 0x88 */
68 uint32_t ifOutErrors; /* 0x8c */
[all …]
/freebsd/sys/arm/arm/
H A Ddisassem.c76 * m - m register (bits 0-3)
81 * h - 3rd fp operand (register/immediate) (bits 0-4)
83 * t - thumb branch address (bits 24, 0-23)
84 * k - breakpoint comment (bits 0-3, 8-19)
87 * c - comment field bits(0-23)
112 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */
113 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */
114 { 0x0f000000, 0x0f000000, "swi", "c" },
115 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */
116 { 0x0f000000, 0x0a000000, "b", "b" },
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h49 0x00000001, 0x00000002, 0x00000004, 0x00000008,
50 0x00000010, 0x00000020, 0x00000040, 0x00000080,
51 0x0000001b, 0x00000036
57 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
58 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
59 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
60 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
61 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
62 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
63 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]

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