Lines Matching +full:0 +full:x0e000000
31 #define ATA_DATA 0 /* (RW) data */
34 #define ATA_F_DMA 0x01 /* enable DMA */
35 #define ATA_F_OVL 0x02 /* enable overlap */
43 #define ATA_D_LBA 0x40 /* use LBA addressing */
44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */
49 #define ATA_E_ILI 0x01 /* illegal length */
50 #define ATA_E_NM 0x02 /* no media */
51 #define ATA_E_ABORT 0x04 /* command aborted */
52 #define ATA_E_MCR 0x08 /* media change request */
53 #define ATA_E_IDNF 0x10 /* ID not found */
54 #define ATA_E_MC 0x20 /* media changed */
55 #define ATA_E_UNC 0x40 /* uncorrectable data */
56 #define ATA_E_ICRC 0x80 /* UDMA crc error */
57 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */
60 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */
61 #define ATA_I_IN 0x02 /* read (1) | write (0) */
62 #define ATA_I_RELEASE 0x04 /* released bus (1) */
63 #define ATA_I_TAGMASK 0xf8 /* tag mask */
67 #define ATA_S_ERROR 0x01 /* error */
68 #define ATA_S_INDEX 0x02 /* index */
69 #define ATA_S_CORR 0x04 /* data corrected */
70 #define ATA_S_DRQ 0x08 /* data request */
71 #define ATA_S_DSC 0x10 /* drive seek completed */
72 #define ATA_S_SERVICE 0x10 /* drive needs service */
73 #define ATA_S_DWF 0x20 /* drive write fault */
74 #define ATA_S_DMA 0x20 /* DMA ready */
75 #define ATA_S_READY 0x40 /* drive ready */
76 #define ATA_S_BUSY 0x80 /* busy */
79 #define ATA_A_IDS 0x02 /* disable interrupts */
80 #define ATA_A_RESET 0x04 /* RESET controller */
81 #define ATA_A_4BIT 0x08 /* 4 head bits */
82 #define ATA_A_HOB 0x80 /* High Order Byte enable */
86 #define ATA_SS_DET_MASK 0x0000000f
87 #define ATA_SS_DET_NO_DEVICE 0x00000000
88 #define ATA_SS_DET_DEV_PRESENT 0x00000001
89 #define ATA_SS_DET_PHY_ONLINE 0x00000003
90 #define ATA_SS_DET_PHY_OFFLINE 0x00000004
92 #define ATA_SS_SPD_MASK 0x000000f0
93 #define ATA_SS_SPD_NO_SPEED 0x00000000
94 #define ATA_SS_SPD_GEN1 0x00000010
95 #define ATA_SS_SPD_GEN2 0x00000020
96 #define ATA_SS_SPD_GEN3 0x00000030
98 #define ATA_SS_IPM_MASK 0x00000f00
99 #define ATA_SS_IPM_NO_DEVICE 0x00000000
100 #define ATA_SS_IPM_ACTIVE 0x00000100
101 #define ATA_SS_IPM_PARTIAL 0x00000200
102 #define ATA_SS_IPM_SLUMBER 0x00000600
103 #define ATA_SS_IPM_DEVSLEEP 0x00000800
106 #define ATA_SE_DATA_CORRECTED 0x00000001
107 #define ATA_SE_COMM_CORRECTED 0x00000002
108 #define ATA_SE_DATA_ERR 0x00000100
109 #define ATA_SE_COMM_ERR 0x00000200
110 #define ATA_SE_PROT_ERR 0x00000400
111 #define ATA_SE_HOST_ERR 0x00000800
112 #define ATA_SE_PHY_CHANGED 0x00010000
113 #define ATA_SE_PHY_IERROR 0x00020000
114 #define ATA_SE_COMM_WAKE 0x00040000
115 #define ATA_SE_DECODE_ERR 0x00080000
116 #define ATA_SE_PARITY_ERR 0x00100000
117 #define ATA_SE_CRC_ERR 0x00200000
118 #define ATA_SE_HANDSHAKE_ERR 0x00400000
119 #define ATA_SE_LINKSEQ_ERR 0x00800000
120 #define ATA_SE_TRANSPORT_ERR 0x01000000
121 #define ATA_SE_UNKNOWN_FIS 0x02000000
122 #define ATA_SE_EXCHANGED 0x04000000
125 #define ATA_SC_DET_MASK 0x0000000f
126 #define ATA_SC_DET_IDLE 0x00000000
127 #define ATA_SC_DET_RESET 0x00000001
128 #define ATA_SC_DET_DISABLE 0x00000004
130 #define ATA_SC_SPD_MASK 0x000000f0
131 #define ATA_SC_SPD_NO_SPEED 0x00000000
132 #define ATA_SC_SPD_SPEED_GEN1 0x00000010
133 #define ATA_SC_SPD_SPEED_GEN2 0x00000020
134 #define ATA_SC_SPD_SPEED_GEN3 0x00000030
136 #define ATA_SC_IPM_MASK 0x00000f00
137 #define ATA_SC_IPM_NONE 0x00000000
138 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100
139 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200
140 #define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400
148 /* SATA AHCI v1.0 register defines */
149 #define AHCI_CAP 0x00
150 #define AHCI_CAP_NPMASK 0x0000001f
151 #define AHCI_CAP_SXS 0x00000020
152 #define AHCI_CAP_EMS 0x00000040
153 #define AHCI_CAP_CCCS 0x00000080
154 #define AHCI_CAP_NCS 0x00001F00
156 #define AHCI_CAP_PSC 0x00002000
157 #define AHCI_CAP_SSC 0x00004000
158 #define AHCI_CAP_PMD 0x00008000
159 #define AHCI_CAP_FBSS 0x00010000
160 #define AHCI_CAP_SPM 0x00020000
161 #define AHCI_CAP_SAM 0x00080000
162 #define AHCI_CAP_ISS 0x00F00000
164 #define AHCI_CAP_SCLO 0x01000000
165 #define AHCI_CAP_SAL 0x02000000
166 #define AHCI_CAP_SALP 0x04000000
167 #define AHCI_CAP_SSS 0x08000000
168 #define AHCI_CAP_SMPS 0x10000000
169 #define AHCI_CAP_SSNTF 0x20000000
170 #define AHCI_CAP_SNCQ 0x40000000
171 #define AHCI_CAP_64BIT 0x80000000
173 #define AHCI_GHC 0x04
174 #define AHCI_GHC_AE 0x80000000
175 #define AHCI_GHC_MRSM 0x00000004
176 #define AHCI_GHC_IE 0x00000002
177 #define AHCI_GHC_HR 0x00000001
179 #define AHCI_IS 0x08
180 #define AHCI_PI 0x0c
181 #define AHCI_VS 0x10
183 #define AHCI_CCCC 0x14
184 #define AHCI_CCCC_TV_MASK 0xffff0000
186 #define AHCI_CCCC_CC_MASK 0x0000ff00
188 #define AHCI_CCCC_INT_MASK 0x000000f8
190 #define AHCI_CCCC_EN 0x00000001
191 #define AHCI_CCCP 0x18
193 #define AHCI_EM_LOC 0x1C
194 #define AHCI_EM_CTL 0x20
195 #define AHCI_EM_MR 0x00000001
196 #define AHCI_EM_TM 0x00000100
197 #define AHCI_EM_RST 0x00000200
198 #define AHCI_EM_LED 0x00010000
199 #define AHCI_EM_SAFTE 0x00020000
200 #define AHCI_EM_SES2 0x00040000
201 #define AHCI_EM_SGPIO 0x00080000
202 #define AHCI_EM_SMB 0x01000000
203 #define AHCI_EM_XMT 0x02000000
204 #define AHCI_EM_ALHD 0x04000000
205 #define AHCI_EM_PM 0x08000000
207 #define AHCI_CAP2 0x24
208 #define AHCI_CAP2_BOH 0x00000001
209 #define AHCI_CAP2_NVMP 0x00000002
210 #define AHCI_CAP2_APST 0x00000004
211 #define AHCI_CAP2_SDS 0x00000008
212 #define AHCI_CAP2_SADM 0x00000010
213 #define AHCI_CAP2_DESO 0x00000020
215 #define AHCI_BOHC 0x28
216 #define AHCI_BOHC_BOS 0x00000001
217 #define AHCI_BOHC_OOS 0x00000002
218 #define AHCI_BOHC_SOOE 0x00000004
219 #define AHCI_BOHC_OOC 0x00000008
220 #define AHCI_BOHC_BB 0x00000010
222 #define AHCI_VSCAP 0xa4
223 #define AHCI_OFFSET 0x100
224 #define AHCI_STEP 0x80
226 #define AHCI_P_CLB 0x00
227 #define AHCI_P_CLBU 0x04
228 #define AHCI_P_FB 0x08
229 #define AHCI_P_FBU 0x0c
230 #define AHCI_P_IS 0x10
231 #define AHCI_P_IE 0x14
232 #define AHCI_P_IX_DHR 0x00000001
233 #define AHCI_P_IX_PS 0x00000002
234 #define AHCI_P_IX_DS 0x00000004
235 #define AHCI_P_IX_SDB 0x00000008
236 #define AHCI_P_IX_UF 0x00000010
237 #define AHCI_P_IX_DP 0x00000020
238 #define AHCI_P_IX_PC 0x00000040
239 #define AHCI_P_IX_MP 0x00000080
241 #define AHCI_P_IX_PRC 0x00400000
242 #define AHCI_P_IX_IPM 0x00800000
243 #define AHCI_P_IX_OF 0x01000000
244 #define AHCI_P_IX_INF 0x04000000
245 #define AHCI_P_IX_IF 0x08000000
246 #define AHCI_P_IX_HBD 0x10000000
247 #define AHCI_P_IX_HBF 0x20000000
248 #define AHCI_P_IX_TFE 0x40000000
249 #define AHCI_P_IX_CPD 0x80000000
251 #define AHCI_P_CMD 0x18
252 #define AHCI_P_CMD_ST 0x00000001
253 #define AHCI_P_CMD_SUD 0x00000002
254 #define AHCI_P_CMD_POD 0x00000004
255 #define AHCI_P_CMD_CLO 0x00000008
256 #define AHCI_P_CMD_FRE 0x00000010
257 #define AHCI_P_CMD_CCS_MASK 0x00001f00
259 #define AHCI_P_CMD_ISS 0x00002000
260 #define AHCI_P_CMD_FR 0x00004000
261 #define AHCI_P_CMD_CR 0x00008000
262 #define AHCI_P_CMD_CPS 0x00010000
263 #define AHCI_P_CMD_PMA 0x00020000
264 #define AHCI_P_CMD_HPCP 0x00040000
265 #define AHCI_P_CMD_MPSP 0x00080000
266 #define AHCI_P_CMD_CPD 0x00100000
267 #define AHCI_P_CMD_ESP 0x00200000
268 #define AHCI_P_CMD_FBSCP 0x00400000
269 #define AHCI_P_CMD_APSTE 0x00800000
270 #define AHCI_P_CMD_ATAPI 0x01000000
271 #define AHCI_P_CMD_DLAE 0x02000000
272 #define AHCI_P_CMD_ALPE 0x04000000
273 #define AHCI_P_CMD_ASP 0x08000000
274 #define AHCI_P_CMD_ICC_MASK 0xf0000000
275 #define AHCI_P_CMD_NOOP 0x00000000
276 #define AHCI_P_CMD_ACTIVE 0x10000000
277 #define AHCI_P_CMD_PARTIAL 0x20000000
278 #define AHCI_P_CMD_SLUMBER 0x60000000
279 #define AHCI_P_CMD_DEVSLEEP 0x80000000
281 #define AHCI_P_TFD 0x20
282 #define AHCI_P_SIG 0x24
283 #define AHCI_P_SSTS 0x28
284 #define AHCI_P_SCTL 0x2c
285 #define AHCI_P_SERR 0x30
286 #define AHCI_P_SACT 0x34
287 #define AHCI_P_CI 0x38
288 #define AHCI_P_SNTF 0x3C
289 #define AHCI_P_FBS 0x40
290 #define AHCI_P_FBS_EN 0x00000001
291 #define AHCI_P_FBS_DEC 0x00000002
292 #define AHCI_P_FBS_SDE 0x00000004
293 #define AHCI_P_FBS_DEV 0x00000f00
295 #define AHCI_P_FBS_ADO 0x0000f000
297 #define AHCI_P_FBS_DWE 0x000f0000
299 #define AHCI_P_DEVSLP 0x44
300 #define AHCI_P_DEVSLP_ADSE 0x00000001
301 #define AHCI_P_DEVSLP_DSP 0x00000002
302 #define AHCI_P_DEVSLP_DETO 0x000003fc
304 #define AHCI_P_DEVSLP_MDAT 0x00007c00
306 #define AHCI_P_DEVSLP_DITO 0x01ff8000
308 #define AHCI_P_DEVSLP_DM 0x0e000000
314 #define AHCI_CL_OFFSET 0
325 #define AHCI_UNIT 0xff /* Channel number. */
330 u_int32_t dbc; /* 0 based */
331 #define AHCI_PRD_MASK 0x003fffff /* max 4MB */
345 #define AHCI_CMD_ATAPI 0x0020
346 #define AHCI_CMD_WRITE 0x0040
347 #define AHCI_CMD_PREFETCH 0x0080
348 #define AHCI_CMD_RESET 0x0100
349 #define AHCI_CMD_BIST 0x0200
350 #define AHCI_CMD_CLR_BUSY 0x0400
358 #define ATA_IRQ_RID 0
512 #define AHCI_IRQ_MODE_ALL 0
597 #define AHCI_Q_NOFORCE 0x00000001
598 #define AHCI_Q_NOPMP 0x00000002
599 #define AHCI_Q_NONCQ 0x00000004
600 #define AHCI_Q_1CH 0x00000008
601 #define AHCI_Q_2CH 0x00000010
602 #define AHCI_Q_4CH 0x00000020
603 #define AHCI_Q_EDGEIS 0x00000040
604 #define AHCI_Q_SATA2 0x00000080
605 #define AHCI_Q_NOBSYRES 0x00000100
606 #define AHCI_Q_NOAA 0x00000200
607 #define AHCI_Q_NOCOUNT 0x00000400
608 #define AHCI_Q_ALTSIG 0x00000800
609 #define AHCI_Q_NOMSI 0x00001000
610 #define AHCI_Q_ATI_PMP_BUG 0x00002000
611 #define AHCI_Q_MAXIO_64K 0x00004000
612 #define AHCI_Q_SATA1_UNIT0 0x00008000 /* need better method for this */
613 #define AHCI_Q_ABAR0 0x00010000
614 #define AHCI_Q_1MSI 0x00020000
615 #define AHCI_Q_FORCE_PI 0x00040000
616 #define AHCI_Q_RESTORE_CAP 0x00080000
617 #define AHCI_Q_NOMSIX 0x00100000
618 #define AHCI_Q_MRVL_SR_DEL 0x00200000
619 #define AHCI_Q_NOCCS 0x00400000
620 #define AHCI_Q_NOAUX 0x00800000
621 #define AHCI_Q_IOMMU_BUSWIDE 0x01000000
622 #define AHCI_Q_SLOWDEV 0x02000000