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/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dwii.dts20 /*/memreserve/ 0x10000000 0x0004000;*/ /* DSP RAM */
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
35 0x10000000 0x04000000>; /* MEM2 64MB GDDR3 */
40 #size-cells = <0>;
42 PowerPC,broadway@0 {
44 reg = <0>;
60 ranges = <0x0c000000 0x0c000000 0x01000000
61 0x0d000000 0x0d000000 0x00800000
62 0x0d800000 0x0d800000 0x00800000>;
68 reg = <0x0c002000 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am64.dtsi54 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
58 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
63 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
H A Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
H A Dk3-j721e-evm-pcie0-ep.dtso34 reg = <0x00 0x02900000 0x00 0x1000>,
35 <0x00 0x02907000 0x00 0x400>,
36 <0x00 0x0d000000 0x00 0x00800000>,
37 <0x00 0x10000000 0x00 0x08000000>;
41 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
48 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
H A Dk3-j722s.dtsi24 #size-cells = <0>;
46 cpu0: cpu@0 {
48 reg = <0x000>;
51 i-cache-size = <0x8000>;
54 d-cache-size = <0x8000>;
58 clocks = <&k3_clks 135 0>;
63 reg = <0x001>;
66 i-cache-size = <0x8000>;
69 d-cache-size = <0x8000>;
73 clocks = <&k3_clks 136 0>;
[all …]
H A Dk3-j784s4-evm-pcie0-pcie1-ep.dtso38 reg = <0x00 0x02900000 0x00 0x1000>,
39 <0x00 0x02907000 0x00 0x400>,
40 <0x00 0x0d000000 0x00 0x00800000>,
41 <0x00 0x10000000 0x00 0x08000000>;
45 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
49 clocks = <&k3_clks 332 0>;
52 max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
60 reg = <0x00 0x02910000 0x00 0x1000>,
61 <0x00 0x02917000 0x00 0x400>,
62 <0x00 0x0d800000 0x00 0x00800000>,
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j722s-main.dtsi12 serdes_refclk: clk-0 {
14 #clock-cells = <0>;
15 clock-frequency = <0>;
22 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
26 clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
37 reg = <0x0f000000 0x00010000>;
39 resets = <&serdes_wiz0 0>;
51 #size-cells = <0>;
60 ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
64 clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
[all …]
/freebsd/sys/contrib/device-tree/src/xtensa/
H A Dcsp.dts11 …bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw e…
14 memory@0 {
16 reg = <0x00000000 0x40000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
36 #clock-cells = <0>;
45 ranges = <0x00000000 0xf0000000 0x10000000>;
47 uart0: serial@0d000000 {
51 reg = <0x0d000000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dti,j721e-pci-ep.yaml127 reg = <0x00 0x02900000 0x00 0x1000>,
128 <0x00 0x02907000 0x00 0x400>,
129 <0x00 0x0d00000
[all...]
H A Ddesignware-pcie.txt46 0x00-0xff is assumed if not present)
55 reg = <0xdfc00000 0x0001000>, /* IP registers */
56 <0xd0000000 0x0002000>; /* Configuration space */
61 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
62 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
70 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
71 <0xdfc01000 0x0001000>, /* IP registers 2 */
72 <0xd0000000 0x2000000>; /* Configuration space */
H A Dti,j721e-pci-host.yaml78 const: 0x104c
82 - 0xb00d
83 - 0xb00f
84 - 0xb010
85 - 0xb012
86 - 0xb013
177 reg = <0x00 0x02900000 0x00 0x1000>,
178 <0x00 0x02907000 0x00 0x400>,
179 <0x00 0x0d000000 0x00 0x00800000>,
180 <0x00 0x10000000 0x00 0x00001000>;
[all …]
H A Dsnps,dw-pcie.yaml55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
83 normally mapped to the 0x0 address of this region, while eDMA
84 is available at 0x80000 base address.
149 pattern: '^dma([0-9]|1[0-5])?$'
222 reg = <0xdfc00000 0x0001000>, /* IP registers */
223 <0xd0000000 0x0002000>; /* Configuration space */
227 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
228 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchFloat64InstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
20 def FADD_D : FP_ALU_3R<0x01010000, FPR64>;
21 def FSUB_D : FP_ALU_3R<0x01030000, FPR64>;
22 def FMUL_D : FP_ALU_3R<0x01050000, FPR64>;
23 def FDIV_D : FP_ALU_3R<0x01070000, FPR64>;
24 def FMADD_D : FP_ALU_4R<0x08200000, FPR64>;
25 def FMSUB_D : FP_ALU_4R<0x08600000, FPR64>;
26 def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>;
27 def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>;
28 def FMAX_D : FP_ALU_3R<0x0109000
[all...]
H A DLoongArchFloat32InstrInfo.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18 : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i64>]>;
20 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f32>]>;
21 def SDT_LoongArchFTINT : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>;
36 def FADD_S : FP_ALU_3R<0x01008000>;
37 def FSUB_S : FP_ALU_3R<0x01028000>;
38 def FMUL_S : FP_ALU_3R<0x01048000>;
39 def FDIV_S : FP_ALU_3R<0x01068000>;
40 def FMADD_S : FP_ALU_4R<0x08100000>;
41 def FMSUB_S : FP_ALU_4R<0x0850000
[all...]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]
/freebsd/sys/dev/qlxgb/
H A Dqla_misc.c54 #define Q8_ADDR_UNDEFINED 0xFFFFFFFF
61 Q8_ADDR_UNDEFINED, /* 0x00 */
62 0x77300000, /* 0x01 */
63 0x29500000, /* 0x02 */
64 0x2A500000, /* 0x03 */
65 Q8_ADDR_UNDEFINED, /* 0x04 */
66 0x0D000000, /* 0x05 */
67 0x1B100000, /* 0x06 */
68 0x0E600000, /* 0x07 */
69 0x0E000000, /* 0x08 */
[all …]
/freebsd/contrib/llvm-project/lld/ELF/
H A DAArch64ErrataFix.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
54 // | 1 | immlo (2) | 1 | 0 0 0 0 | immhi (19) | Rd (5) |
56 return (instr & 0x9f000000) == 0x90000000; in isADRP()
63 // All loads and stores have 1 (at bit position 27), (0 at bit position 25).
64 // | op0 x op1 (2) | 1 op2 0 op3 (2) | x | op4 (5) | xxxx | op5 (2) | x (10) |
66 return (instr & 0x0a000000) == 0x08000000; in isLoadStoreClass()
70 // | 0 Q 00 | 1100 | 0 L 00 | 0000 | opcode (4) | size (2) | Rn (5) | Rt (5) |
72 // | 0 Q 00 | 1100 | 1 L 0 | Rm (5)| opcode (4) | size (2) | Rn (5) | Rt (5) |
73 // L == 0 for stores.
82 return (instr & 0x0000f000) == 0x00002000 || in isST1MultipleOpcode()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nvidia/
H A Dtegra124.dtsi21 reg = <0x0 0x80000000 0x0 0x0>;
27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
28 <0x0 0x0100380
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra132.dtsi22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34 bus-range = <0x00 0xff>;
38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
[all …]
/freebsd/sys/dev/ral/
H A Drt2860.c70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
243 sc->sc_debug = 0; in rt2860_attach()
248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); in rt2860_attach()
252 for (ntries = 0; ntries < 100; ntries++) { in rt2860_attach()
254 if (tmp != 0 && tmp != 0xffffffff) in rt2860_attach()
265 sc->mac_rev = tmp & 0xffff; in rt2860_attach()
267 if (sc->mac_ver != 0x2860 && in rt2860_attach()
268 (id == 0x0681 || id == 0x0781 || id == 0x1059)) in rt2860_attach()
273 device_printf(sc->sc_dev, "MAC/BBP RT%X (rev 0x%04X), " in rt2860_attach()
[all …]
/freebsd/sys/dev/usb/wlan/
H A Dif_run.c84 int run_debug = 0;
85 static SYSCTL_NODE(_hw_usb, OID_AUTO, run, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
87 SYSCTL_INT(_hw_usb_run, OID_AUTO, debug, CTLFLAG_RWTUN, &run_debug, 0,
91 RUN_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
92 RUN_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
93 RUN_DEBUG_RECV = 0x00000004, /* basic recv operation */
94 RUN_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
95 RUN_DEBUG_STATE = 0x00000010, /* 802.11 state transitions */
96 RUN_DEBUG_RATE = 0x00000020, /* rate adaptation */
97 RUN_DEBUG_USB = 0x00000040, /* usb requests */
[all …]

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