54 #define Q8_ADDR_UNDEFINED		0xFFFFFFFF
61 		Q8_ADDR_UNDEFINED,	/* 0x00 */
62 		0x77300000,		/* 0x01 */
63 		0x29500000,		/* 0x02 */
64 		0x2A500000,		/* 0x03 */
65 		Q8_ADDR_UNDEFINED,	/* 0x04 */
66 		0x0D000000,		/* 0x05 */
67 		0x1B100000,		/* 0x06 */
68 		0x0E600000,		/* 0x07 */
69 		0x0E000000,		/* 0x08 */
70 		0x0E100000,		/* 0x09 */
71 		0x0E200000,		/* 0x0A */
72 		0x0E300000,		/* 0x0B */
73 		0x42000000,		/* 0x0C */
74 		0x41700000,		/* 0x0D */
75 		0x42100000,		/* 0x0E */
76 		0x34B00000,		/* 0x0F */
77 		0x40500000,		/* 0x10 */
78 		0x34000000,		/* 0x11 */
79 		0x34100000,		/* 0x12 */
80 		0x34200000,		/* 0x13 */
81 		0x34300000,		/* 0x14 */
82 		0x34500000,		/* 0x15 */
83 		0x34400000,		/* 0x16 */
84 		0x3C000000,		/* 0x17 */
85 		0x3C100000,		/* 0x18 */
86 		0x3C200000,		/* 0x19 */
87 		0x3C300000,		/* 0x1A */
88 		Q8_ADDR_UNDEFINED,	/* 0x1B */
89 		0x3C400000,		/* 0x1C */
90 		0x41000000,		/* 0x1D */
91 		Q8_ADDR_UNDEFINED,	/* 0x1E */
92 		0x0D100000,		/* 0x1F */
93 		Q8_ADDR_UNDEFINED,	/* 0x20 */
94 		0x77300000,		/* 0x21 */
95 		0x41600000,		/* 0x22 */
96 		Q8_ADDR_UNDEFINED,	/* 0x23 */
97 		Q8_ADDR_UNDEFINED,	/* 0x24 */
98 		Q8_ADDR_UNDEFINED,	/* 0x25 */
99 		Q8_ADDR_UNDEFINED,	/* 0x26 */
100 		Q8_ADDR_UNDEFINED,	/* 0x27 */
101 		0x41700000,		/* 0x28 */
102 		Q8_ADDR_UNDEFINED,	/* 0x29 */
103 		0x08900000,		/* 0x2A */
104 		0x70A00000,		/* 0x2B */
105 		0x70B00000,		/* 0x2C */
106 		0x70C00000,		/* 0x2D */
107 		0x08D00000,		/* 0x2E */
108 		0x08E00000,		/* 0x2F */
109 		0x70F00000,		/* 0x30 */
110 		0x40500000,		/* 0x31 */
111 		0x42000000,		/* 0x32 */
112 		0x42100000,		/* 0x33 */
113 		Q8_ADDR_UNDEFINED,	/* 0x34 */
114 		0x08800000,		/* 0x35 */
115 		0x09100000,		/* 0x36 */
116 		0x71200000,		/* 0x37 */
117 		0x40600000,		/* 0x38 */
118 		Q8_ADDR_UNDEFINED,	/* 0x39 */
119 		0x71800000,		/* 0x3A */
120 		0x19900000,		/* 0x3B */
121 		0x1A900000,		/* 0x3C */
122 		Q8_ADDR_UNDEFINED,	/* 0x3D */
123 		0x34600000,		/* 0x3E */
124 		Q8_ADDR_UNDEFINED,	/* 0x3F */
136 	{(0x088 << 20), (0x035 << 20)},
137 	{(0x089 << 20), (0x02A << 20)},
138 	{(0x08D << 20), (0x02E << 20)},
139 	{(0x08E << 20), (0x02F << 20)},
140 	{(0x0C6 << 20), (0x023 << 20)},
141 	{(0x0C7 << 20), (0x024 << 20)},
142 	{(0x0C8 << 20), (0x025 << 20)},
143 	{(0x0D0 << 20), (0x005 << 20)},
144 	{(0x0D1 << 20), (0x01F << 20)},
145 	{(0x0E0 << 20), (0x008 << 20)},
146 	{(0x0E1 << 20), (0x009 << 20)},
147 	{(0x0E2 << 20), (0x00A << 20)},
148 	{(0x0E3 << 20), (0x00B << 20)},
149 	{(0x0E6 << 20), (0x007 << 20)},
150 	{(0x199 << 20), (0x03B << 20)},
151 	{(0x1B1 << 20), (0x006 << 20)},
152 	{(0x295 << 20), (0x002 << 20)},
153 	{(0x29A << 20), (0x000 << 20)},
154 	{(0x2A5 << 20), (0x003 << 20)},
155 	{(0x340 << 20), (0x011 << 20)},
156 	{(0x341 << 20), (0x012 << 20)},
157 	{(0x342 << 20), (0x013 << 20)},
158 	{(0x343 << 20), (0x014 << 20)},
159 	{(0x344 << 20), (0x016 << 20)},
160 	{(0x345 << 20), (0x015 << 20)},
161 	{(0x3C0 << 20), (0x017 << 20)},
162 	{(0x3C1 << 20), (0x018 << 20)},
163 	{(0x3C2 << 20), (0x019 << 20)},
164 	{(0x3C3 << 20), (0x01A << 20)},
165 	{(0x3C4 << 20), (0x01C << 20)},
166 	{(0x3C5 << 20), (0x01B << 20)},
167 	{(0x405 << 20), (0x031 << 20)},
168 	{(0x406 << 20), (0x038 << 20)},
169 	{(0x410 << 20), (0x01D << 20)},
170 	{(0x416 << 20), (0x022 << 20)},
171 	{(0x417 << 20), (0x028 << 20)},
172 	{(0x420 << 20), (0x032 << 20)},
173 	{(0x421 << 20), (0x033 << 20)},
174 	{(0x700 << 20), (0x00C << 20)},
175 	{(0x701 << 20), (0x00D << 20)},
176 	{(0x702 << 20), (0x00E << 20)},
177 	{(0x703 << 20), (0x00F << 20)},
178 	{(0x704 << 20), (0x010 << 20)},
179 	{(0x70A << 20), (0x02B << 20)},
180 	{(0x70B << 20), (0x02C << 20)},
181 	{(0x70C << 20), (0x02D << 20)},
182 	{(0x70F << 20), (0x030 << 20)},
183 	{(0x718 << 20), (0x03A << 20)},
184 	{(0x758 << 20), (0x026 << 20)},
185 	{(0x759 << 20), (0x027 << 20)},
186 	{(0x773 << 20), (0x001 << 20)}
190 #define Q8_ADDR_MASK		(0xFFF << 20)
209 	offset = (addr & 0xFFF00000) >> 20;  in qla_rdwr_indreg32()
211 	if (offset > 0x3F) {  in qla_rdwr_indreg32()
212 		device_printf(ha->pci_dev, "%s: invalid addr 0x%08x\n",  in qla_rdwr_indreg32()
219 		device_printf(ha->pci_dev, "%s: undefined map 0x%08x\n",  in qla_rdwr_indreg32()
224 	offset = offset | (addr & 0x000F0000);  in qla_rdwr_indreg32()
226 	if (qla_sem_lock(ha, Q8_SEM7_LOCK, 0, 0)) {  in qla_rdwr_indreg32()
244 		*val = READ_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000));  in qla_rdwr_indreg32()
246 		WRITE_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000), *val);  in qla_rdwr_indreg32()
250 	return 0;  in qla_rdwr_indreg32()
272 		WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_CTRL, 0x07); /* Write */  in qla_rdwr_offchip_mem()
274 		WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_CTRL, 0x03); /* Read */  in qla_rdwr_offchip_mem()
290 			return 0;  in qla_rdwr_offchip_mem()
295 	device_printf(ha->pci_dev, "%s: failed[0x%08x]\n", __func__, data);  in qla_rdwr_offchip_mem()
309 	if (qla_sem_lock(ha, Q8_SEM2_LOCK, 0, 0)) {  in qla_rd_flash32()
313 	WRITE_OFFSET32(ha, Q8_ROM_LOCKID, 0xa5a5a5a5);  in qla_rd_flash32()
316 	qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);  in qla_rd_flash32()
317 	val = 0;  in qla_rd_flash32()
318 	qla_rdwr_indreg32(ha, Q8_ROM_DUMMY_BYTE_COUNT, &val, 0);  in qla_rd_flash32()
320 	qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_rd_flash32()
325 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_rd_flash32()
335 	val = 0;  in qla_rd_flash32()
336 	qla_rdwr_indreg32(ha, Q8_ROM_DUMMY_BYTE_COUNT, &val, 0);  in qla_rd_flash32()
337 	qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_rd_flash32()
344 	return 0;  in qla_rd_flash32()
350         if (qla_sem_lock(ha, Q8_SEM2_LOCK, 0, 0)) {  in qla_p3p_sem_lock2()
354         WRITE_OFFSET32(ha, Q8_ROM_LOCKID, 0xa5a5a5a5);  in qla_p3p_sem_lock2()
355         return (0);  in qla_p3p_sem_lock2()
371 	for (i = 0; i < crb_to_pci_table_size; i++) {  in qla_int_to_pci_addr_map()
389 		(addr == 0x00112040) ||  in qla_filter_pci_addr()
390 		(addr == 0x00112048) ||  in qla_filter_pci_addr()
391 		((addr & 0xFFFF0FFF) == 0x001100C4) ||  in qla_filter_pci_addr()
392 		((addr & 0xFFFF0FFF) == 0x001100C8) ||  in qla_filter_pci_addr()
393 		((addr & 0x0FF00000) == 0x00200000) ||  in qla_filter_pci_addr()
394 		(addr == 0x022021FC) ||  in qla_filter_pci_addr()
395 		(addr == 0x0330001C) ||  in qla_filter_pci_addr()
396 		(addr == 0x03300024) ||  in qla_filter_pci_addr()
397 		(addr == 0x033000A8) ||  in qla_filter_pci_addr()
398 		(addr == 0x033000C8) ||  in qla_filter_pci_addr()
399 		(addr == 0x033000BC) ||  in qla_filter_pci_addr()
400 		((addr & 0x0FF00000) == 0x03A00000) ||  in qla_filter_pci_addr()
401 		(addr == 0x03B0001C))  in qla_filter_pci_addr()
410  *	Essentially reads the address/value pairs from address = 0x00 and
416 	uint32_t val = 0, sig = 0;  in qla_crb_init()
420 	qla_rd_flash32(ha, 0, &sig);  in qla_crb_init()
421 	QL_DPRINT2((ha->pci_dev, "%s: val[0] = 0x%08x\n", __func__, sig));  in qla_crb_init()
424 	QL_DPRINT2((ha->pci_dev, "%s: val[4] = 0x%08x\n", __func__, val));  in qla_crb_init()
427 	offset = val & 0xFFFF;  in qla_crb_init()
430 	QL_DPRINT2((ha->pci_dev, "%s: [sig,val]=[0x%08x, 0x%08x] %d pairs\n",  in qla_crb_init()
440 	memset(avmap, 0, (sizeof(addr_val_t) * count));  in qla_crb_init()
443 	for (i = 0; i < count; ) {  in qla_crb_init()
453 			"%s: [0x%02x][0x%08x:0x%08x:0x%08x] 0x%08x\n",  in qla_crb_init()
458 			qla_rdwr_indreg32(ha, avmap->ind_addr, &avmap->value,0);  in qla_crb_init()
465 	return (0);  in qla_crb_init()
475 	WRITE_OFFSET32(ha, Q8_PEG_D_RESET1, 0x001E);  in qla_init_peg_regs()
476 	WRITE_OFFSET32(ha, Q8_PEG_D_RESET2, 0x0008);  in qla_init_peg_regs()
477 	WRITE_OFFSET32(ha, Q8_PEG_I_RESET, 0x0008);  in qla_init_peg_regs()
478 	WRITE_OFFSET32(ha, Q8_PEG_0_CLR1, 0x0000);  in qla_init_peg_regs()
479 	WRITE_OFFSET32(ha, Q8_PEG_0_CLR2, 0x0000);  in qla_init_peg_regs()
480 	WRITE_OFFSET32(ha, Q8_PEG_1_CLR1, 0x0000);  in qla_init_peg_regs()
481 	WRITE_OFFSET32(ha, Q8_PEG_1_CLR2, 0x0000);  in qla_init_peg_regs()
482 	WRITE_OFFSET32(ha, Q8_PEG_2_CLR1, 0x0000);  in qla_init_peg_regs()
483 	WRITE_OFFSET32(ha, Q8_PEG_2_CLR2, 0x0000);  in qla_init_peg_regs()
484 	WRITE_OFFSET32(ha, Q8_PEG_3_CLR1, 0x0000);  in qla_init_peg_regs()
485 	WRITE_OFFSET32(ha, Q8_PEG_3_CLR2, 0x0000);  in qla_init_peg_regs()
486 	WRITE_OFFSET32(ha, Q8_PEG_4_CLR1, 0x0000);  in qla_init_peg_regs()
487 	WRITE_OFFSET32(ha, Q8_PEG_4_CLR2, 0x0000);  in qla_init_peg_regs()
497 	uint64_t mem_off	= 0x10000;  in qla_load_fw_from_flash()
498 	uint32_t flash_off	= 0x10000;  in qla_load_fw_from_flash()
503 	for (count = 0; count < 0x20000 ; ) {  in qla_load_fw_from_flash()
520 		qla_rdwr_offchip_mem(ha, mem_off, &val, 0);  in qla_load_fw_from_flash()
554 	WRITE_OFFSET32(ha, Q8_CMDPEG_STATE, 0x00000000);  in qla_init_from_flash()
555 	WRITE_OFFSET32(ha, Q8_PEG_0_RESET, 0x00001020);  in qla_init_from_flash()
556 	WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0x0080001E);  in qla_init_from_flash()
562 		QL_DPRINT2((ha->pci_dev, "%s: func[%d] cmdpegstate 0x%08x\n",  in qla_init_from_flash()
568 			return(0);  in qla_init_from_flash()
574 		"%s: func[%d] Q8_PEG_HALT_STATUS1[0x%08x] STATUS2[0x%08x]"  in qla_init_from_flash()
575 		" HEARTBEAT[0x%08x] RCVPEG_STATE[0x%08x]"  in qla_init_from_flash()
576 		" CMDPEG_STATE[0x%08x]\n",  in qla_init_from_flash()
594         int ret = 0;  in qla_init_hw()
603 	if (ha->pci_func & 0x1) {  in qla_init_hw()
604         	while ((ha->pci_func & 0x1) && delay--) {  in qla_init_hw()
629 		if (qla_rd_flash32(ha, 0x100004, &val) == 0) {  in qla_init_hw()
630 			if (((val & 0xFF) != ha->fw_ver_major) ||  in qla_init_hw()
631 				(((val >> 8) & 0xFF) != ha->fw_ver_minor) ||  in qla_init_hw()
632 				(((val >> 16) & 0xFF) != ha->fw_ver_sub)) {  in qla_init_hw()
660 			return 0;  in qla_wait_for_flash_busy()
671 	val = 0;  in qla_flash_write_enable()
672 	qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_flash_write_enable()
675 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_write_enable()
690 	if (qla_flash_write_enable(ha) != 0)   in qla_flash_unprotect()
693 	val = 0;  in qla_flash_unprotect()
694 	qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);  in qla_flash_unprotect()
697 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_unprotect()
706 	if (qla_flash_write_enable(ha) != 0)   in qla_flash_unprotect()
709 	val = 0;  in qla_flash_unprotect()
710 	qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);  in qla_flash_unprotect()
713 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_unprotect()
728 	if (qla_flash_write_enable(ha) != 0)   in qla_flash_protect()
731 	val = 0x9C;  in qla_flash_protect()
732 	qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);  in qla_flash_protect()
735 	qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_protect()
752 		val = 0;  in qla_flash_get_status()
753 		qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_flash_get_status()
756 		qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_get_status()
760 		if (rval == 0) {  in qla_flash_get_status()
763 			if ((val & BIT_0) == 0)  in qla_flash_get_status()
777 		if (qla_flash_get_status(ha) == 0)  in qla_wait_for_flash_unprotect()
778 			return 0;  in qla_wait_for_flash_unprotect()
792 		if (qla_flash_get_status(ha) == 0x9C)  in qla_wait_for_flash_protect()
793 			return 0;  in qla_wait_for_flash_protect()
807 	if (qla_flash_write_enable(ha) != 0)   in qla_erase_flash_sector()
811         qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);  in qla_erase_flash_sector()
814         qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_erase_flash_sector()
817         qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_erase_flash_sector()
826 #define Q8_FLASH_SECTOR_SIZE 0x10000
830 	int rval = 0;  in qla_erase_flash()
845 	for (start = off; start < (off + size); start = start + 0x10000) {  in qla_erase_flash()
865 	int rval = 0;  in qla_flash_write32()
868         qla_rdwr_indreg32(ha, Q8_ROM_WR_DATA, &val, 0);  in qla_flash_write32()
871         qla_rdwr_indreg32(ha, Q8_ROM_ADDRESS, &val, 0);  in qla_flash_write32()
874         qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_flash_write32()
877         qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_write32()
891 	int rval = 0;  in qla_flash_wait_for_write_complete()
894 		val = 0;  in qla_flash_wait_for_write_complete()
895 		qla_rdwr_indreg32(ha, Q8_ROM_ADDR_BYTE_COUNT, &val, 0);  in qla_flash_wait_for_write_complete()
898 		qla_rdwr_indreg32(ha, Q8_ROM_INSTR_OPCODE, &val, 0);  in qla_flash_wait_for_write_complete()
903 		if (rval == 0) {  in qla_flash_wait_for_write_complete()
906 			if ((val & BIT_0) == 0)  in qla_flash_wait_for_write_complete()
907 				return (0);  in qla_flash_wait_for_write_complete()
917 	if (qla_flash_write_enable(ha) != 0)   in qla_flash_write()
920 	if (qla_flash_write32(ha, off, data) != 0)  in qla_flash_write()
926 	return 0;  in qla_flash_write()
933 	int rval = 0;  in qla_flash_write_pattern()
954 	if (rval == 0)  in qla_flash_write_pattern()
968 	int rval = 0;  in qla_flash_write_data()
983 		if (*data32 != 0xFFFFFFFF) {  in qla_flash_write_data()
994 	if (rval == 0)  in qla_flash_write_data()
1008 	int rval = 0;  in qla_wr_flash_buffer()
1011 	if (size == 0)  in qla_wr_flash_buffer()
1012 		return 0;  in qla_wr_flash_buffer()